ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 144

• Manufacturer Part Number: ST10F269Z2Q6
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Controller Family/series: ST10
• No. Of I/o's: 111
• Ram Memory Size: 12KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Embedded Interface Type: CAN, SSC, USART
• Rohs Compliant: Yes
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4833

21.3.1 - A/D Converter Characteristics
V
V
Table 41 : A/D Converter Characteristics
Notes: 1. V
144/184
V
V
I
C
t
t
DNL
INL
OFS
TUE
R
K
AGND
AREF
S
C
DD
AREF
AIN
AIN
ASRC
= 5V ± 10%, V
Symbol
X000h or X3FFh, respectively.
2. During the t
the analog source must allow the capacitance to reach its final voltage level within the t
time, changes of the analog input voltage have no effect on the conversion result. Values for the t
programming. Referring to the t
Table 42 on page 145:
- t
- t
TCL is defined in Section 21.4.2 -, Section 21.4.4 -, and Section 21.4.5 - ‘Direct Drive’ on page 149:
3. The conversion time formula is:
- t
The t
the result of the conversion. Values for the t
- t
- t
4. This parameter is fixed by ADC control logic.
5. DNL, INL, TUE are tested at V
voltages within the defined voltage range.
‘LSB’ has a value of V
The specified TUE is guaranteed only if an overload condition (see
pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA.
6. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channel with an
absolute overload current less than 10mA.
7. Partially tested, guaranteed by design characterization.
8.To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at
the ADC input. The cut-off frequency of this filter should avoid 2 opposite transitions during the t
- f
where t
S
S
C
C
C
cut-off
min. = 2 t
max = 2 t
= 14 t
min. = 14 t
max = 14 t
AIN
V
C
SS
parameter includes the t
SR
SR
CC
CC
CC
CC
CC
CC
CC
CC
SR
CC
s
may exceed V
is the sampling time of the ST10 ADC and is not related to the Nyquist frequency determined by the t
CC
+ 0.2V
1 / 5 t
+ t
SC
SC
S
CC
CC
S
sample time the input capacitance C
s
min. = 2 t
max = 2 x 8 t
Analog Reference voltage
Analog input voltage
Reference supply current
running mode
power-down mode
ADC input capacitance
Not sampling
Sampling
Sample time
Conversion time
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Total unadjusted error
Internal resistance of analog source
Coupling Factor between inputs
+ 4 TCL (= 14 t
min. + t
max + t
to 1/10 t
SS
AREF
AGND
= 0V
S
S
CC
s
min. + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL
/ 1024.
or V
min. = 2 x 24 x TCL = 48 TCL
,
CC
T
S
A
CC
max = 2 x 8 x 96 TCL = 1536 TCL
AREF
C
Parameter
sample time, the time for determining the digital result and the time to load the result register with
= -40 to +85°C or -40 to +125°C, 4.0V
conversion time formula of Section 21.3.2 - ‘Conversion Timing Control’ on page 145 and to
AREF
+ 2 t
up to the absolute maximum ratings. However, the conversion result in these cases will be
SC
= 5.0V, V
CC
+ 4 TCL)
conversion clock depend on the programming. Referring to Table 42 on page 145:
AGND
ain
can be charged/discharged by the external source. The internal resistance of
= 0V, V
CC
1 - 8
7
7
2 - 4
3 - 4
5
5
5
5
t
6 - 7
Test Condition
S
= 4.9V. It is guaranteed by design characterization for all other
I
in [ns]
OV
specification) occurs on maximum 2 not selected analog input
2 - 7
4.0
V
–
–
–
–
48 TCL
388 TCL
-0.5
-1.5
-1.0
-2.0
–
–
minimum
S
AGND
sample time. After the end of the t
V
AREF
Limit Values
s
sampling time of the ST10 ADC:
SC
V
V
V
500
1
10
15
1 536 TCL
2 884 TCL
+0.5
+1.5
+1.0
+2.0
(t
1/500
DD
AREF
S
sample clock depend on the
DD
maximum
/ 150) - 0.25
+ 0.1
+ 0.1V; V
c
conversion time.
ST10F269
SS
S
0.1V
Unit
LSB
LSB
LSB
LSB
sample
k
pF
pF
V
V
A
A