ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 183

• Manufacturer Part Number: ST10F269Z2Q6
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Controller Family/series: ST10
• No. Of I/o's: 111
• Ram Memory Size: 12KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Embedded Interface Type: CAN, SSC, USART
• Rohs Compliant: Yes
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4833

ST10F269
2.4 - ST_PORT.3 - Bad Behavior of Hysteresis Function on Input Falling Edge
In the following conditions, a slow falling edge on a ST10F269 input may generate multiple events :
– A falling edge is occuring.
– AND the falling edge has a transition time between Vih and Vil longer than the CPU clock period.
Workaround:
Add external hardware on the ST10 input in order to have a fast falling edge (lower than 1/Fcpu).
History of Fixed Functional Problems of the ST10F269Zxxx-D
Summary of Remaining Functional Problems Known on the ST10F269Zxxx-D
3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION
Note on on-chip oscillator
The XTAL2 output is not designed to provide a valid signal when XTAL1 is supplied by an external clock
signal. It may happen, if the external clock signal is not perfectly symetrical and centered on V
XTAL2 signal is not equal to XTAL1. This is due to the design of the oscillator, which has a auto-adapta-
tion gain control dedicated to external crystal.
If an external clock signal is directly provided on XTAL1 pin, then leave XTAL2 pin disconnected to
achieve the lowest consumption of the on-chip oscillator.
4 - ERRATA SHEET VERSION INFORMATION
This document was released in September 2003. It reflects the current silicon status of the
ST10F269Zxxx-D.
Modification
Name of the
ST_PORT.3
ST_PORT.2
PWRDN.1
MAC.10
MAC.9
Name
Input signal
(falling edge)
Internal
signal
(t2 - t1) > 1/Fcpu
E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled
Wrong Port Direction after Return From Power Down Mode
Execution of PWRDN Instruction
CoCMP Instruction Inverted Operands
Bad Behavior of Hysteresis Function on Input Falling Edge
3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION
“1”
Vih
t1
Short Description
PROBLEM
Short Description
t2
Vil
“0”
Fixed in Step
DD
D
/ 2, that
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