ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 67

• Manufacturer Part Number: ST10F269Z2Q6
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Controller Family/series: ST10
• No. Of I/o's: 111
• Ram Memory Size: 12KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Embedded Interface Type: CAN, SSC, USART
• Rohs Compliant: Yes
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4833

ST10F269
Figure 23 : PORT1 I/O and Alternate Functions
When an external bus mode is enabled, the
direction of the port pin and the loading of data
into the port output latch are controlled by the bus
controller hardware.
The input of the port Buffer latch is disconnected
from the internal bus and is switched to the line
labeled “Alternate Data Output” via a multiplexer.
The alternate data is the 16-bit intra-segment
Figure 24 : Block Diagram of a PORT1 Pin
PORT1
General Purpose Input/Output
Alternate Function
P1H
P1L
Write DP1H.y / DP1L.y
Read DP1H.y / DP1L.y
Write P1H.y / P1L.y
Read P1H.y / P1L.y
Port Output
P1H.7
P1H.6
P1H.5
P1H.4
P1H.3
P1H.2
P1H.1
P1H.0
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
P1L.1
P1L.0
Direction
Latch
Latch
MUX
8/16-bit Demultiplexed Bus
Port Data
Output
1
0
Alternate
Function
Enable
Alternate
Data
Output
“1”
a)
address. While an external bus mode is enabled,
the user software should not write to the port
output latch, otherwise unpredictable results may
occur. When the external bus modes are disabled,
the contents of the direction register last written by
the user becomes active.
The Figure 24 shows the structure of a PORT1
pin.
1
0
1
0
MUX
MUX
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Clock
Latch
Input
CAPCOM2 Capture Inputs only
Output
Buffer
12 - PARALLEL PORTS
b)
CC27IO
CC26IO
CC25IO
CC24IO
y = 7...0
P1H.y
P1L.y
67/184