ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 23

• Manufacturer Part Number: ST10F269Z2Q6
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Controller Family/series: ST10
• No. Of I/o's: 111
• Ram Memory Size: 12KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Embedded Interface Type: CAN, SSC, USART
• Rohs Compliant: Yes
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4833

ST10F269
If the second command given is not an erase
confirm or if the coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Mode. It is not necessary to program the block
with 0000h as the EPC will do this automatically
before the erasing to FFFFh. Read operations
after the EPC has started, output the Flash Status
Register.
During the execution of the erase by the EPC, the
device accepts only the Erase Suspend and
Read/Reset instructions. Data Polling bit FSB.7
returns ‘0’ while the erasure is in progress, and ‘1’
when it has completed. The Toggle bit FSB.2 and
FSB.6 toggle during the erase operation. They
stop when erase is completed. After completion,
the Error bit FSB.5 returns ‘1’ if there has been an
erase failure because erasure has not completed
even after the maximum number of erase cycles
have been executed by the EPC, in this case, it
will be necessary to input a Read/Reset to the
Command Interface in order to reset the EPC.
Chip Erase (CE). This instruction uses six write
cycles. The Erase Enable command xx80h, must
be written at address 1554h after CI-Enable
cycles. The Chip Erase command xx10h must be
given on the sixth cycle after a second CI-Enable
sequence. An error in command sequence will
reset the CI to Read mode. It is NOT necessary to
program the block with 0000h as the EPC will do
this automatically before the erasing to FFFFh.
Read operations after the EPC has started output
the Flash Status Register. During the execution of
the erase by the EPC, Data Polling bit FSB.7
returns ‘0’ while the erasure is in progress, and ‘1’
when it has completed. The FSB.2 and FSB.6 bit
toggle during the erase operation. They stop when
erase is finished. The FSB.5 error bit returns "1" in
case of failure of the erase operation. The error
flag is set after the maximum number of erase
cycles have been executed by the EPC. In this
case, it will be necessary to input a Read/Reset to
the Command Interface in order to reset the EPC.
Erase Suspend (ES). This instruction can be
used to suspend a Block Erase operation by
giving the command xxB0h without any specific
address. No CI-Enable cycles is required. Erase
Suspend operation allows reading of data from
another block and/or the programming in another
block while erase is in progress. If this command
is given during the time-out period, it will terminate
the time-out period in addition to erase Suspend.
The Toggle bit FSB.6, when monitored at an
address that belongs to the block being erased,
stops toggling when Erase Suspend Command is
effective, It happens between 0.1 s and 15 s
after the Erase Suspend Command has been
written. The Flash will then go in normal Read
Mode, and read from blocks not being erased is
valid, while read from block being erased will
output FSB.2 toggling. During a Suspend phase
the only instructions valid are Erase Resume and
Program Word. A Read / Reset instruction during
Erase suspend will definitely abort the Erase and
result in invalid data in the block being erased.
Erase Resume (ER). This instruction can be
given when the memory is in Erase Suspend
State. Erase can be resumed by writing the
command xx30h at any address without any
Cl-enable sequence.
Program during Erase Suspend. The Program
Word instruction during Erase Suspend is allowed
only on blocks that are not Erase-suspended. This
instruction is the same than the Program Word
instruction.
Set Protection (SP). This instruction can be used
to enable both Block Protection (to protect each
block independently from accidental Erasing-Pro-
gramming Operation) and Code Protection (to
avoid code dump). The Set Protection Command
must be given after a special CI-Protection Enable
cycles (see instruction table). The following Write
cycle, will program the Protection Register. To pro-
tect the block x (x = 0 to 6), the data bit x must be
at ‘0’. To protect the code, bit 15 of the data must
be ‘0’. Enabling Block or Code Protection is per-
manent and can be cleared only by STM. Block
Temporary Unprotection and Code Temporary
Unprotection instructions are available to allow the
customer to update the code.
Notes: 1.
Read Protection Status (RP). This instruction is
used to read the Block Protection status and the
Code Protection status. To read the protection
register (see Table 3), the CI-Protection Enable
cycles must be executed followed by the
command
following Read Cycles at any odd word address
will output the Block Protection Status. The Read/
Reset command xxF0h must be written to reset
the protection interface.
Note: After a modification of protection register
(using Set Protection command), the Read
protection register will only become active
after a reset.
2. Bit that are already at ’0’ in protection
register must be confirmed at ’0’ also in
data latched during the 4th cycle of set
protection command, otherwise an error
may occur.
The
5 - INTERNAL FLASH MEMORY
xx90h
new
at
value
address x2A54h. The
programmed
23/184
in