MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 178

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Clock Module
9.6.2.2
The SYNSR is a read-only register that can be read at any time. Writing to the SYNSR has no effect and
terminates the cycle normally.
9-8
Note: 1. Reset state determined during reset configuration.
Bit(s)
3–2
1–0
7
6
5
4
Address
2. See the LOCKS and LOCK bit descriptions.
Reset
Synthesizer Status Register (SYNSR)
Field PLLMODE PLLSEL
R/W
DISCLK
FWKUP
LOCEN
STPMD
Name
—
—
7
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
See note 1
Table 9-4. SYNCR Field Descriptions (continued)
Enables the loss-of-clock function. LOCEN does not affect the loss of lock function.
1 Loss-of-clock function enabled
0 Loss-of-clock function disabled
Note: In external clock mode, the LOCEN bit has no effect
Disable CLKOUT determines whether CLKOUT is driven. Setting the DISCLK bit
holds CLKOUT low.
1 CLKOUT disabled
0 CLKOUT enabled
Fast wakeup determines when the system clocks are enabled during wakeup from
stop mode.
1 System clocks enabled on wakeup regardless of PLL lock status
0 System clocks enabled only when PLL is locked or operating normally
Note: When FWKUP = 0, if the PLL or oscillator is enabled and unintentionally lost in
stop mode, the PLL wakes up in self-clocked mode or reference clock mode
depending on the clock that was lost. In external clock mode, the FWKUP bit has no
effect on the wakeup sequence.
Reserved, should be cleared.
Control PLL and CLKOUT operation in stop mode. The following table illustrates
STPMD operation in stop mode.
Reserved, should be cleared.
Figure 9-4. Synthesizer Status Register (SYNSR)
6
STPMD[1:0]
00
01
10
11
PLLREF
5
Disabled
Disabled
Disabled
Disabled
System
Clocks
IPSBAR + 0x0012_0002
LOCKS
4
See note 2
R
Disabled
Disabled
Enabled
Enabled
Operation During Stop Mode
Description
PLL
LOCK
3
LOCS
Disabled
Enabled
Enabled
Enabled
OSC
2
.
000
Freescale Semiconductor
1
CLKOUT
Disabled
Disabled
Disabled
Enabled
—
0