MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 312

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Fast Ethernet Controller (FEC)
The descriptor controller is a RISC-based controller providing these functions in the FEC:
The RAM is the focal point of all data flow in the Fast Ethernet controller and divides into transmit and
receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from
the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the
transmit block, and receive data flows from the receive block into the receive FIFO.
17-2
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•
•
•
•
Initialization (those internal registers not initialized by you or hardware)
High level control of the DMA channels (initiating DMA transfers)
Interpreting buffer descriptors
Address recognition for receive frames
Random number generation for transmit collision backoff timer
microcode)
Descriptor
Controller
Controller
(RISC +
Bus
Internal Bus
Internal Bus
DMA references in this section refer to the FEC’s DMA engine. This DMA
engine transfers FEC data only and is not related to the eDMA controller
described in
described in
Interface
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Chapter 16, “DMA Controller Module,”
Chapter 21, “DMA Timers (DTIM0–DTIM3).”
Control/Status
Registers
FEC_MDIO
MDEN
MDO
Figure 17-1. FEC Block Diagram
PAD
I/O
MII
Counter RAM
MDI
FEC_MDC
MIB
NOTE
FEC_TXEN
FEC_TXD[3:0]
FEC_TXER
Interface
FIFO
RAM
RAM
Transmit
MII/7-Wire data
FEC_TXCLK
FEC_CRS
FEC_COL
nor to the DMA timers
option
Controller
FIFO
FEC_RXCLK
FEC_RXDV
FEC_RXD[3:0]
FEC_RXER
Receive
Crossbar Switch
Master Bus
Freescale Semiconductor
FEC DMA
FEC Bus