MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 334

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Fast Ethernet Controller (FEC)
17.4.23 Transmit Buffer Descriptor Ring Start Registers (ETSDR)
ETSDR provides a pointer to the start of the circular transmit buffer descriptor queue in external memory.
This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly
divisible by 16). You should write zeros to bits 1 and 0. Hardware ignores non-zero values in these two bit
positions.
This register is undefined at reset and must be initialized prior to operation.
17.4.24 Receive Buffer Size Register (EMRBR)
The EMRBR is a user-programmable register that dictates the maximum size of all receive buffers. This
value should take into consideration that the receive CRC is always written into the last receive buffer. To
allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. To properly
align the buffer, EMRBR must be evenly divisible by 16. To ensure this, bits 3–0 are forced low.
17-24
R_DES_START
X_DES_START
Field
31–2
Field
31–2
1–0
1–0
IPSBAR
IPSBAR
Offset:
Offset:
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
W
W
R
R
0x1180
0x1184
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Pointer to start of receive buffer descriptor queue.
Reserved, must be cleared.
Pointer to start of transmit buffer descriptor queue.
Reserved, must be cleared.
Figure 17-22. Ethernet Receive Descriptor Ring Start Register (ERDSR)
Figure 17-23. Transmit Buffer Descriptor Ring Start Register (ETDSR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 17-26. ERDSR Field Descriptions
Table 17-27. ETDSR Field Descriptions
R_DES_START
X_DES_START
Description
Description
8
8
7
7
Access: User read/write
Access: User read/write
6
6
Freescale Semiconductor
5
5
4
4
3
3
2
2
0
0
1
1
0
0
0
0