MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 555
MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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28.6.6
This subsection describes the QADC status registers.
28.6.6.1 QADC Status Register 0 (QASR0)
QASR0 contains information about the state of each queue and the current A/D conversion. The bits in
this register are read anytime. For flag bits (CF1, PF1, CF2, PF2, TOR1, TOR2), writing a 1 has no effect;
writing a 0 clears the bit. For QS[9:6] and CWP, writes have no effect. Stop mode resets this register.
The end of a queue is identified in the following cases:
Freescale Semiconductor
•
•
When execution is complete on the CCW in the location prior to the one
pointed to by BQ2
When the current CCW contains the end-of-queue code (channel 63) instead of a valid channel
number
Status Registers
MQ2[12:8]
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 28-9. Queue 2 Operating Modes (continued)
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Reserved mode
Reserved mode
Software triggered continuous-scan mode
Externally triggered rising edge continuous-scan mode
Externally triggered falling edge continuous-scan mode
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Reserved mode
Operating Modes
Queued Analog-to-Digital Converter (QADC)
13
14
15
16
17
7
8
9
10
11
12
13
14
15
16
17
28-17
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