MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 425

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

23.3.1
The UMR1n registers control UART module configuration. UMR1n can be read or written when the mode
register pointer points to it, at RESET or after a
UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
Freescale Semiconductor
RXIRQ/
RXRTS
FFULL
Field
ERR
4–3
PM
7
6
5
IPSBAR
Offset:
Reset:
Receiver request-to-send. Allows the URTSn output to control the UCTSn input of the transmitting device to prevent
receiver overrun. If the receiver and transmitter are incorrectly programmed for URTSn control, URTSn control is
disabled for both. Transmitter RTS control is configured in UMR2n[TXRTS].
0 The receiver has no effect on URTSn.
1 When a valid start bit is received, URTSn is negated if the UART's FIFO is full. URTSn is reasserted when the
Receiver interrupt select.
0 RXRDY is the source generating interrupt or DMA requests.
1 FFULL is the source generating interrupt or DMA requests.
Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].
0 Character mode. The USRn values reflect the status of the character at the top of the FIFO. ERR must be 0 for
1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of the FIFO since
Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character,
and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below.
W
R
FIFO has an empty position available.
correct A/D flag information when in multidrop mode.
the last
Registers
UART Mode Registers 1 (UMR1n)
0x00_0200 (UMR10)
0x00_0240 (UMR11)
0x00_0280 (UMR12)
1
RXRTS
After UMR1n is read or written, the pointer points to UMR2n
0
7
RESET ERROR STATUS
(UCRn).”
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
RXIRQ/
FFULL
6
0
Figure 23-3. UART Mode Registers 1 (UMR1n)
Table 23-3. UMR1n Field Descriptions
command for the UART was issued. See
ERR
0
5
RESET MODE REGISTER POINTER
0
4
Description
PM
0
3
Section 23.3.5, “UART Command
PT
0
2
command using
Access: User read/write
0
1
B/C
UART Modules
0
0
1
23-5