MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 546

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Queued Analog-to-Digital Converter (QADC)
28.6.2
The QADCTEST is a reserved register. Attempts to access this register outside of factory test mode will
result in access privilege violation.
28.6.3
QADC ports QA and QB are accessed through the 8-bit PORTQA and PORTQB.
Port QA signals are referred to as PQA[4:3, 1:0] when used as a bidirectional, 4-bit, input/output port. Port
QA can also be used for analog inputs (AN[56:55, 53:52]), external trigger inputs (ETRIG[2:1]), and
external multiplexer address outputs (MA[1:0]).
Port QB signals are referred to as PQB[3:0] when used as a 4-bit, digital input-only port. Port QB can also
be used for non-multiplexed (AN[3:0]) and multiplexed (ANZ, ANY, ANX, ANW) analog inputs.
PORTQA and PORTQB are not initialized by reset.
28-8
Bit(s)
13–8
Address
6–0
15
14
7
Reset
R/W:
Field
QADC Test Register (QADCTEST)
Port Data Registers (PORTQA & PORTQB)
QSTOP
QDBG
Name
SUPV
7
—
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 28-4. QADC Port QA Data Register (PORTQA)
000
—
R
6
Stop enable.
1 Force QADC to idle state.
0 QADC operates normally.
Debug enable.
1 Finish any conversion in progress, then freeze in debug mode
0 QADC operates normally.
Reserved, should be cleared.
Supervisor/unrestricted data space.
1 All QADC registers are accessible in supervisor mode only; user mode accesses
0 Only QADCMCR and QADCTEST require supervisor mode access; access to all
Reserved, should be cleared.
Table 28-3. QADCMCR Field Descriptions
have no effect and result in a cycle termination error.
other QADC registers is unrestricted
5
(ETRIG2)
IPSBAR + 0x19_0006
(AN56)
PQA4
4
See Note
R/W
(ETRIG1)
(AN55)
PQA3
Description
3
—
R
0
2
(AN53)
(MA1)
PQA1
1
Freescale Semiconductor
See Note
R/W
(AN52)
PQA0
(MA0)
0