MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 635

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

The assertion of BKPT should be considered in the following two special cases:
CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt conditions.
Freescale Semiconductor
1. A catastrophic fault-on-fault condition automatically halts the processor.
2. A hardware breakpoint can be configured to generate a pending halt condition similar to the
3. The execution of a HALT instruction immediately suspends execution. Attempting to execute
4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition is
•
•
assertion of BKPT. This type of halt is always first made pending in the processor. Next, the
processor samples for pending halt and interrupt conditions once per instruction. When a pending
condition is asserted, the processor halts execution at the next sample point. See
“Theory of
HALT in user mode while CSR[UHE] = 0 generates a privilege violation exception. If
CSR[UHE] = 1, HALT can be executed in user mode. After HALT executes, the processor can be
restarted by serial shifting a
instruction after HALT.
postponed until the processor core samples for halts/interrupts. The processor samples for these
conditions once during the execution of each instruction. If there is a pending halt condition at the
sample time, the processor suspends execution and enters the halted state.
After the system reset signal is negated, the processor waits for 16 processor clock cycles before
beginning reset exception processing. If the BKPT input is asserted within eight cycles after RSTI
is negated, the processor enters the halt state, signaling halt status (0xF) on the PST outputs. While
the processor is in this state, all resources accessible through the debug module can be referenced.
This is the only chance to force the processor into emulation mode through CSR[EMU].
After system initialization, the processor’s response to the
BDM commands performed while it is halted for a breakpoint. Specifically, if the PC register was
loaded, the
address in the PC, bypassing normal reset exception processing. If the PC was not loaded, the
command causes the processor to exit halted state and continue reset exception processing.
The ColdFire architecture also handles a special case of BKPT being asserted while the processor
is stopped by execution of the STOP instruction. For this case, the processor exits the stopped mode
and enters the halted state, at which point, all BDM commands may be exercised. When restarted,
the processor continues by executing the next sequential instruction, that is, the instruction
following the STOP opcode.
GO
Operation.”
command causes the processor to exit halted state and pass control to the instruction
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
GO
command into the debug module. Execution continues at the
GO
command depends on the set of
Section 30.6.1,
Debug Support
30-17
GO