MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 215

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Chapter 12
Chip Select Module
This chapter describes the chip select module, including the operation and programming model of the chip
select registers, which include the chip select address, mask, and control registers.
12.1
The following list summarizes the key chip select features:
12.2
Table 12-1
Table 12-2
Freescale Semiconductor
•
•
Chip Selects
(CS[6:0])
Output Enable
(OE)
Byte Strobes
BS[3:0]
Up to seven independent, user-programmable chip select signals (CS[6:0]) that can interface with
external SRAM, PROM, EPROM, EEPROM, Flash, and peripherals
Address masking for 64-Kbyte to 4-Gbyte memory block sizes
Signal
Overview
Chip Select Module Signals
lists signals used by the chip select module.
shows the interaction of the byte-enable/byte-write enables with related signals.
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used
for the bus.
Each CSn can be independently programmed for an address location as well as for masking, port
size, read/write burst capability, wait-state generation, and internal/external termination. Only CS0 is
initialized at reset and may act as an external boot chip select to allow boot ROM to be at an external
address space. Port size for CS0 is configured by the logic levels of D[19:18] when RSTO negates
and RCON is asserted.
Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and negated
on the falling edge of the clock. OE is asserted only when one of the chip selects matches for the
current address decode.
These signals are individually programmed through the byte-enable mode bit, CSCRn[BEM],
described in
These generated signals provide byte data select signals, which are decoded from the transfer size,
A1, and A0 signals in addition to the programmed port size and burstability of the memory accessed,
as
Table 12-2
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Section 12.4.1.3, “Chip Select Control Registers
shows.
Table 12-1. Chip Select Module Signals
NOTE
Description
(CSCR0–CSCR6)”.
12-1