HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 519

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
13.3.2
Areas
Area 0: For area 0, external address bits A28 to A26 are 000.
SRAM, MPX, and burst ROM can be set to this area.
A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins
MD4 and MD3. For details, see Memory Bus Width in section 13.1.5, Overview of Areas.
When area 0 is accessed, the CS0 signal is asserted. In addition, the RD signal, which can be used
as OE, and write control signals WE0 to WE7, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A0W2 to A0W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (RDY).
When the burst ROM interface is used, the number of burst cycle transfer states is selected in the
range 2 to 9 according to the number of waits.
The read/write strobe signal address and the CS setup/hold time can be set, respectively, to 0 or 1
and to 0 to 3 cycles using the A0S0, A0H1, and A0H0 bits in the WCR3 register.
Area 1: For area 1, external address bits A28 to A26 are 001.
SRAM, MPX and byte control SRAM can be set to this area.
A bus width of 8, 16, 32, or 64 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2
register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits
A1SZ1 and A1SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus
width of 16, 32, or 64 bits.
When area 1 is accessed, the CS1 signal is asserted. In addition, the RD signal, which can be used
as OE, and write control signals WE0 to WE7, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A1W2 to A1W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (RDY).
The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A1S0 and bits A1H1 and A1H0 in the WCR3
register.
Rev.7.00 Oct. 10, 2008 Page 433 of 1074
REJ09B0366-0700