HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 567

Manufacturer Part Number

HD6417750RF240DV

MPU 3V 16K I-TEMP,PB-FREE 208-QF

Manufacturer

Renesas Electronics America

SuperH® SH7750r

Core Processor

Connectivity

EBI/EMI, FIFO, SCI, SmartCard

DMA, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Oscillator Type

Operating Temperature

-40°C ~ 85°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

Data Converters

Manufacturer

Part Number:

HD6417750RF240DV

Manufacturer:

Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between

an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the

DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally

divided into two or four banks, after a READ or WRIT command is issued for one bank it is

possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch

cycle, or during the data write cycle, and so shorten the access cycle.

Precharge-sel

(SA: IO → memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.37 Burst Write Timing (Different Row Addresses)

Rev.7.00 Oct. 10, 2008 Page 481 of 1074

Section 13 Bus State Controller (BSC)

REJ09B0366-0700