HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 718

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
4. Handshake protocol without use of the data bus
5. Direct data transfer mode (valid on channel 2 only)
6. Request queue transfer request acceptance
Rev.7.00 Oct. 10, 2008 Page 632 of 1074
REJ09B0366-0700
b. If, during execution of the handshake protocol using the data bus for channel 0, a request is
c. In the SH7750S and SH7750R, initial settings can be made in the DMAC channel 0 control
a. With the handshake protocol without use of the data bus, a DMA transfer request can be
b. When using the handshake protocol without use of the data bus, first make the necessary
c. When not using the handshake protocol without use of the data bus, if TR only is asserted
d. If TR only is asserted by means of the handshake protocol without use of the data bus and a
a. If a DMA transfer request for channel 2 is input by simultaneous assertion of DBREQ and
b. In direct data transfer mode (with DBREQ and TR asserted simultaneously), DBREQ is not
a. The DDT has four request queues for each of channels 1 to 3. When these request queues
b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus
input for one of channels 1 to 3, and after that DMA transfer is executed settings of
DTR.ID = 00, DTR.MD = 00, and DTR, SZ ≠ 101.110 are input in the handshake protocol
using the data bus, a transfer request will be asserted for channel 0.
register from the CPU (possible settings are CHCR0.RS = 0000, 0010, or 0011). If settings
of DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101 or 110 are subsequently input, a
transfer request to channel 0 will be asserted.
input to the DMAC again for the channel for which transfer was requested immediately
before by asserting TR only.
settings in the DMAC control registers.
without outputting DTR, a request will be issued for the channel for which DMA transfer
was requested immediately before. Also, if the first DMA transfer request after a power-on
reset is input by asserting TR only, it will be ignored and the DMAC will not operate.
DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE =
1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be
cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1.
TR during DMA transfer execution with the handshake protocol without use of the data
bus, it will be accepted if there is space in the DDT channel 2 request queue.
interpreted as a bus arbitration signal, and therefore the BAVL signal is never asserted.
are full, a DMA transfer request from an external device will be ignored.
cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished
(burst mode) or that a DMA bus cycle is not in progress (cycle steal mode).