HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 73

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
Figure 15.1 Block Diagram of SCI............................................................................................ 657
Figure 15.2 MD0/SCK Pin ........................................................................................................ 674
Figure 15.3 MD7/TxD Pin......................................................................................................... 675
Figure 15.4 RxD Pin.................................................................................................................. 675
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Figure 15.6 Relation between Output Clock and Transfer Data Phase
Figure 15.7 Sample SCI Initialization Flowchart ...................................................................... 690
Figure 15.8 Sample Serial Transmission Flowchart .................................................................. 691
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
Figure 15.10 Sample Serial Reception Flowchart (1).................................................................. 694
Figure 15.10 Sample Serial Reception Flowchart (2).................................................................. 695
Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity,
Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart ......................................... 700
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)......................................... 704
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2)......................................... 705
Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor
Figure 15.17 Data Format in Synchronous Communication ....................................................... 707
Figure 15.18 Sample SCI Initialization Flowchart ...................................................................... 709
Figure 15.19 Sample Serial Transmission Flowchart .................................................................. 710
Figure 15.20 Example of SCI Transmit Operation ...................................................................... 712
Figure 15.21 Sample Serial Reception Flowchart (1).................................................................. 713
Figure 15.21 Sample Serial Reception Flowchart (2).................................................................. 714
Figure 15.22 Example of SCI Receive Operation........................................................................ 715
Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception ............................ 716
Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode ....................................... 720
Figure 15.25 Example of Synchronous Transmission by DMAC ............................................... 721
Figure 15.26 Example Countermeasure on SH7750.................................................................... 723
Figure 15.27 Clock Input Timing of SCK Pin............................................................................. 723
Parity, Two Stop Bits) ............................................................................................ 687
(Asynchronous Mode)............................................................................................ 689
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 693
One Stop Bit).......................................................................................................... 697
(Transmission of Data H'AA to Receiving Station A) ........................................... 699
Bit, One Stop Bit)................................................................................................... 702
Bit, One Stop Bit)................................................................................................... 706
Rev.7.00 Oct. 10, 2008 Page lxxi of lxxxiv
REJ09B0366-0700