HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 540

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Burst Access: In addition to the normal DRAM access mode in which a row address is output in
each data access, a fast page mode is also provided for the case where consecutive accesses are
made to the same row. This mode allows fast access to data by outputting the row address only
once, then changing only the column address for each subsequent access. Normal access or burst
access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The
timing for burst access using fast page mode is shown in figure 13.19.
If the access size exceeds the set bus width, burst access is performed. In a 32-byte burst transfer
(cache fill), the first access comprises a longword that includes the data requiring access. The
remaining accesses are performed on 32-byte boundary data that includes the relevant data. In
burst transfer (cache write-back), wraparound writing is performed for 32-byte data.
Rev.7.00 Oct. 10, 2008 Page 454 of 1074
REJ09B0366-0700
CKIO
A25–A0
CSn
RD/WR
RAS
CAS
D63–D0
(read)
D63–D0
(write)
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Tr1
Figure 13.19 DRAM Burst Access Timing
r
Tr2
Tc1
d1
c1
Tc2
d1
Tc1
c2
d2
Tc2
d2
Tc1
c3
d3
Tc2
d3
Tc1
c4
d4
Tc2
d4
Tpc