HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 843

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

16.3
16.3.1
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is
achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details.
Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed. RTS2 and CTS2 signals
are also provided as modem control signals.
The transmission format is selected using the serial mode register (SCSMR2), as shown in table
16.3. The SCIF clock source is determined by the CKE1 bit in the serial control register
(SCSCR2), as shown in table 16.4.
• Data length: Choice of 7 or 8 bits
• Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters
• Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receive-
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Choice of internal or external clock as SCIF clock source
determines the transfer format and character length)
data-ready state, and breaks, during reception
When internal clock is selected: The SCIF operates on the baud rate generator clock, and can
output a clock with a frequency of 16 times the bit rate.
When external clock is selected: A clock with a frequency of 16 times the bit rate must be
input (the on-chip baud rate generator is not used).
Operation
Overview
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev.7.00 Oct. 10, 2008 Page 757 of 1074
REJ09B0366-0700