HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 776

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
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7 287
Section 15 Serial Communication Interface (SCI)
Serial Data Transmission (Asynchronous Mode): Figure 15.8 shows a sample flowchart for
serial transmission.
Use the following procedure for serial data transmission after enabling the SCI for transmission.
Rev.7.00 Oct. 10, 2008 Page 690 of 1074
REJ09B0366-0700
Set TE and RE bits in SCSCR1
to 1, and set RIE, TIE, TEIE,
in SCSCR1 (leaving TE and
Set transmit/receive format
Set CKE1 and CKE0 bits
1-bit interval elapsed?
Set value in SCBRR1
Clear TE and RE bits
RE bits cleared to 0)
in SCSCR1 to 0
and MPIE bits
Initialization
in SCSMR1
End
Yes
Figure 15.7 Sample SCI Initialization Flowchart
Wait
No
1. Set the clock selection in SCSCR1.
2. Set the transmit/receive format in
3. Write a value corresponding to the
4. Wait at least one bit interval, then set
Be sure to clear bits RIE, TIE, TEIE,
and MPIE, and bits TE and RE, to 0.
When clock output is selected in
asynchronous mode, it is output
immediately after SCSCR1 settings
are made.
SCSMR1.
bit rate into SCBRR1. (Not
necessary if an external clock is
used.)
the TE bit or RE bit in SCSCR1 to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
When transmitting, the SCI will go to
the mark state; when receiving, it will
go to the idle state, waiting for a start
bit.

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