HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 632

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
• An interrupt request can be sent to the CPU on completion of the specified number of
• Transfer requests: The following three DMAC transfer activation requests are supported.
• Channel functions: Transfer modes that can be set are different for each channel.
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transfers.
⎯ External request
⎯ Requests from on-chip peripheral modules
⎯ Auto-request
⎯ Normal DMA mode
(1) Normal DMA mode
(2) On-demand data transfer mode (DDT mode)
Transfer requests from the SCI, SCIF, and TMU. These can be accepted on all channels.
The transfer request is generated automatically within the DMAC.
•
•
Channel 0: Single or dual address mode. External requests are accepted.
Channel 1: Single or dual address mode. External requests are accepted.
From two DREQ pins. Either low level detection or falling edge detection can be
specified. External requests can be accepted on channels 0 and 1 only.
In this mode of the SH7750 and SH7750S, interfacing between an external device and
the DMAC is performed using the DBREQ, BAVL, TR, TDACK, ID [1:0], and D
[63:0] pins. External requests can be accepted on all four channels.
In the SH7750R, the DBREQ, BAVL, TR, TDACK, ID [2:0], and D [63:0] pins are
used as the interface between an external device and the DMAC. External requests can
be accepted on any of the eight channels.
For channel 0, data transfer can be carried out with the transfer mode, number of
transfers, transfer address (single only), etc., specified by the external device.
Although channel 0 has no request queue, there are four request queues for each of the
other channels: i.e., channels 1 to 3 in the SH7750 or SH7750S, and channels 1 to 7 in
the SH7750R.
In the SH7750R, request queues can be cleared on a channel-by-channel basis in DDT
mode in either of the following two ways.
• Clearing a request queue by DTR format
• Using software to clear the request queue
Note: * DTR.COUNT [7:4] (DTR [55:52]): Sets the port as not used.
The request queues of the relevant channel are cleared when it receives DTR.SZ =
110, DTR.ID = 00, DTR.MD = 11, and DTR.COUNT [7:4]* = [1−8].
The request queues of the relevant channel are cleared by writing a 1 to the
CHCRn.QCL bit (request-queue clear bit) of each channel.