HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 731

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. For details of the
settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
14.7.5
Initial value:
Initial value:
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. For details
of the settings, see the description of the DDT bit in section 14.2.5, DMA Operation Register
(DMAOR)
Bit 14⎯Number of DDT-Mode Channels (DBL): Selects the number of channels that are able
to accept external requests in DDT mode.
Bit 14: DBL
0
1
Note: When DMAOR.DBL = 0, channels 4 to 7 cannot accept external requests.
When DMAOR.DBL = 1, one channel can be selected from among channels 0−7 by the
combination of DTR.SZ and DTR.ID in the DTR format (see figure 14.54). Table 14.14 shows the
channel selection by DTR format in the DDT mode.
R/W:
R/W: R/W R/W
Bit:
Bit:
DMA Operation Register (DMAOR)
DDT DBL
31
15
R
0
0
30
14
R
Description
Four DDT-mode channels
Eight DDT-mode channels
0
0
29
13
—
R
R
0
0
28
12
—
R
R
0
0
27
11
—
R
R
0
0
26
10
—
R
R
0
0
Section 14 Direct Memory Access Controller (DMAC)
R/W R/W
PR1 PR0
25
R
0
9
0
24
R
0
8
0
Rev.7.00 Oct. 10, 2008 Page 645 of 1074
23
—
R
R
0
7
0
22
—
R
R
0
6
0
21
—
R
R
0
5
0
20
—
R
R
0
4
0
19
—
R
R
0
3
0
REJ09B0366-0700
R/(W) R/(W) R/W
AE NMIF DME
18
R
0
2
0
(Initial value)
17
R
0
1
0
16
R
0
0
0