ATMEGA169-16AI SL710 Atmel, ATMEGA169-16AI SL710 Datasheet - Page 119

• Manufacturer Part Number: ATMEGA169-16AI SL710
• Description: IC AVR MCU 16K 16MHZ IND 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16AI SL710

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA16916ASL710

Table 58. Waveform Generation Mode Bit Description
Note:
Timer/Counter1 Control
Register B – TCCR1B
2514P–AVR–07/06
Mode
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the
WGM13
location of these bits are compatible with previous versions of the timer.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WGM12
(CTC1)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(PWM11)
WGM11
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise can-
celer is activated, the input from the Input Capture pin (ICP1) is filtered. The filter
function requires four successive equal valued samples of the ICP1 pin for changing its
output. The Input Capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a cap-
ture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as
trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the
capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied
into the Input Capture Register (ICR1). The event will also set the Input Capture Flag
Bit
Read/Write
Initial Value
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
(PWM10)
WGM10
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICNC1
R/W
7
0
(1)
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase and Frequency
Correct
PWM, Phase and Frequency
Correct
PWM, Phase Correct
PWM, Phase Correct
CTC
(Reserved)
Fast PWM
Fast PWM
ICES1
R/W
6
0
R
5
–
0
WGM13
WGM
R/W
4
0
12:0 definitions. However, the functionality and
WGM12
R/W
3
0
TOP
0xFFFF
0x00FF
0x01FF
0x03FF
OCR1A
0x00FF
0x01FF
0x03FF
ICR1
OCR1A
ICR1
OCR1A
ICR1
–
ICR1
OCR1A
CS12
R/W
2
0
ATmega169/V
Update of
OCR1
Immediate
TOP
TOP
TOP
Immediate
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
TOP
TOP
Immediate
–
BOTTOM
BOTTOM
CS11
R/W
1
0
x
at
CS10
R/W
0
0
TOV1 Flag
Set on
MAX
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
MAX
–
TOP
TOP
TCCR1B
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