ATMEGA169-16AI SL710 Atmel, ATMEGA169-16AI SL710 Datasheet - Page 239

• Manufacturer Part Number: ATMEGA169-16AI SL710
• Description: IC AVR MCU 16K 16MHZ IND 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16AI SL710

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA16916ASL710

Scanning the Clock Pins
2514P–AVR–07/06
The AVR devices have many clock options selectable by fuses. These are: Internal RC
Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal
Oscillator, and Ceramic Resonator.
Figure 112 shows how each Oscillator with external connection is supported in the scan
chain. The Enable signal is supported with a general Boundary-scan cell, while the
Oscillator/clock output is attached to an observe-only cell. In addition to the main clock,
the timer Oscillator is scanned in the same way. The output from the internal RC Oscilla-
tor is not scanned, as this Oscillator does not have external connections.
Figure 112. Boundary-scan Cells for Oscillators and Clock Options
Table 103 summaries the scan registers for the external clock pin XTAL1, oscillators
with XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Table 103. Scan Signals for the Oscillator
Notes:
Enable Signal
EXTCLKEN
OSCON
OSC32EN
From Digital Logic
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,
between the internal Oscillator and the JTAG TCK clock. If possible, scanning an
external clock is preferred.
the clock configuration is considered fixed for a given application. The user is advised
to scan the same clock option as to be used in the final system. The enable signals
are supported in the scan chain because the system logic can disable clock options
in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not
provided.
Previous
From
Cell
ShiftDR
0
1
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
ClockDR
D
UpdateDR
Q
Next
Cell
To
D
G
Q
EXTEST
0
1
XTAL1/TOSC1
Clock Option
External Clock
External Crystal
External Ceramic Resonator
Low Freq. External Crystal
(1)(2)(3)
ENABLE
Oscillator
XTAL2/TOSC2
OUTPUT
Previous
From
Cell
ATmega169/V
ShiftDR
0
1
ClockDR
D
FF1
Scanned Clock
Line when not
Q
Next
Cell
To
Used
1
0
1
To System Logic
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