ATMEGA169-16AI SL710 Atmel, ATMEGA169-16AI SL710 Datasheet - Page 149

• Manufacturer Part Number: ATMEGA169-16AI SL710
• Description: IC AVR MCU 16K 16MHZ IND 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16AI SL710

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA16916ASL710

2514P–AVR–07/06
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL func-
tionality is summarized below:
Table 67. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 67 and Figure 68 for an example.
The CPOL functionality is summarized below:
Table 68. CPHA Functionality
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency f
Table 69. Relationship Between SCK and the Oscillator Frequency
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
0
1
0
1
osc
is shown in the following table:
SPR1
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
ATmega169/V
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
149