ATMEGA169-16AI SL710 Atmel, ATMEGA169-16AI SL710 Datasheet - Page 43

• Manufacturer Part Number: ATMEGA169-16AI SL710
• Description: IC AVR MCU 16K 16MHZ IND 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16AI SL710

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA16916ASL710

Watchdog Timer
Watchdog Timer Control
Register – WDTCR
2514P–AVR–07/06
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at
1 MHz. This is the typical value at V
at other V
interval can be adjusted as shown in Table 21 on page 44. The WDR – Watchdog Reset
– instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is
disabled and when a Chip Reset occurs. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another
Watchdog Reset, the ATmega169 resets and executes from the Reset Vector. For tim-
ing details on the Watchdog Reset, refer to Table 21 on page 44.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out
period, two different safety levels are selected by the fuse WDTON as shown in Table
20. Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer”
on page 45 for details.
Table 20. WDT Configuration as a Function of the Fuse Settings of WDTON
Figure 20. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega169 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This
bit must also be set when changing the prescaler bits. See “Timed Sequences for
Changing the Configuration of the Watchdog Timer” on page 45.
Bit
Read/Write
Initial Value
WDTON
Unprogrammed
Programmed
CC
levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset
R
7
–
0
Safety
Level
1
2
OSCILLATOR
WATCHDOG
R
6
–
0
WDT Initial
State
Disabled
Enabled
R
5
–
0
CC
= 5V. See characterization data for typical values
WDCE
R/W
4
0
How to Disable the
WDT
Timed sequence
Always enabled
WDE
R/W
3
0
WDP2
R/W
2
0
ATmega169/V
WDP1
R/W
1
0
How to Change
Time-out
Timed sequence
Timed sequence
WDP0
R/W
0
0
WDTCR
43