ATMEGA169-16AI SL710 Atmel, ATMEGA169-16AI SL710 Datasheet - Page 56

• Manufacturer Part Number: ATMEGA169-16AI SL710
• Description: IC AVR MCU 16K 16MHZ IND 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169-16AI SL710

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA16916ASL710

Ports as General Digital
I/O
Configuring the Pin
56
ATmega169/V
Note that enabling the alternate function of some of the port pins does not affect the use
of the other pins in the port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a
functional description of one I/O-port pin, here generically called Pxn.
Figure 23. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O-Ports” on page 76, the DDxn bits are accessed at the
DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at
the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-
ured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when
reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an out-
put pin, the port pin is driven low (zero).
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clk
I/O
PUD:
SLEEP:
clk
I/O
, SLEEP, and PUD are common to all ports.
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
(1)
SLEEP
SYNCHRONIZER
D
L
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
D
PINxn
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
PUD
clk
WDx
RDx
RPx
1
0
I/O
2514P–AVR–07/06
WPx
WRx