MRF89XA-I/MQ Microchip Technology, MRF89XA-I/MQ Datasheet - Page 29

TXRX ISM SUB-GHZ ULP 32QFN

MRF89XA-I/MQ

Manufacturer Part Number
MRF89XA-I/MQ
Description
TXRX ISM SUB-GHZ ULP 32QFN
Manufacturer
Microchip Technology
Datasheets

Specifications of MRF89XA-I/MQ

Package / Case
32-WFQFN Exposed Pad
Frequency
863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
Data Rate - Maximum
200kbps
Modulation Or Protocol
FSK, OOK
Applications
ISM
Power - Output
12.5dBm
Sensitivity
-113dBm
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
3mA
Current - Transmitting
25mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
863 MHz to 870 MHz, 902 MHz to 928 MHz, 950 MHz to 960 MHz
Interface Type
SPI
Noise Figure
- 112 dBc
Output Power
- 8.5 dBm, + 12.5 dBm
Operating Supply Voltage
2.1 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Data Rate
256 Kbps
Maximum Supply Current
25 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MRF89XA-I/MQ
Manufacturer:
MICROCHIP
Quantity:
12 000
FIGURE 2-18:
The
command, configuration, control, status or data/FIFO
fields as listed in Table 2-6. The registers operate on
parameters common to transmit and receive modes,
Interrupts, Sync pattern, crystal oscillator and packets.
The FIFO serves as a buffer for data transmission and
reception. There is a shifted register (SR) to handle bit
shifts for the FIFO during transmission and reception.
POR sets default values in all Configuration/Control
/Status registers.
© 2010 Microchip Technology Inc.
MRF89XA
registers
0x0C
0x0D
0x0A
0x0B
0x0E
0x0F
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
MRF89XA REGISTERS MEMORY MAP
Register Name
FTXRXIREG
GCONREG
DMODREG
FIFOCREG
RSTHIREG
FTPRIREG
FDEVREG
FLTHREG
BRSREG
R1CREG
P1CREG
S1CREG
R2CREG
P2CREG
S2CREG
PACREG
functionally
handles
Preliminary
0x1C
0x1D
0x1A
0x1B
0x1E
0x1F
0x10
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x11
Register Name
SYNCV31REG
SYNCV23REG
SYNCV15REG
SYNCV07REG
TXCONREG
NADDSREG
PLOADREG
OOKCREG
SYNCREG
CLKOREG
FCRCREG
RSTSREG
PKTCREG
FILCREG
RSVREG
PFCREG
MRF89XA
DS70622B-page 29

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