MRF89XA-I/MQ Microchip Technology, MRF89XA-I/MQ Datasheet - Page 54

• Manufacturer Part Number: MRF89XA-I/MQ
• Description: TXRX ISM SUB-GHZ ULP 32QFN
• Manufacturer: Microchip Technology

Specifications of MRF89XA-I/MQ

• Package / Case: 32-WFQFN Exposed Pad
• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 863 MHz to 870 MHz, 902 MHz to 928 MHz, 950 MHz to 960 MHz
• Interface Type: SPI
• Noise Figure: - 112 dBc
• Output Power: - 8.5 dBm, + 12.5 dBm
• Operating Supply Voltage: 2.1 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Data Rate: 256 Kbps
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.20
2.20.1
REGISTER 2-29:
2.20.2
REGISTER 2-30:
DS70622B-page 54
MRF89XA
bit 7
R = Readable bit
-n = Value at POR
r = Reserved
bit 7
bit 6-0
bit 7
R = Readable bit
-n = Value at POR
r = Reserved
bit 7-0
MCHSTREN
R/W-0
R/W-0
Packet Configuration Registers
PAYLOAD CONFIGURATION
REGISTER DETAILS
NODE ADDRESS SET REGISTER
DETAILS
MCHSTREN: Manchester Encoding/Decoding Enable bit
1 = Enabled
0 = Disabled (default)
PLDPLEN<6:0>: Payload Packet Length bits
These bits indicate payload packet length. If Pkt_format = 0, payload length. If Pkt_format = 1, max
length in RX, not used in TX.
PLDPLEN<6:0> = 000000 (default)
NLADDR<7:0>: Node Local Address bits
These bits are to be set to configure the Node Local Address for filtering of received packets.
NLADDR<7:0> = 00h (default)
R/W-0
R/W-0
PLOADREG: PAYLOAD CONFIGURATION REGISTER
(ADDRESS:0x1C) (POR:0x00)
NADDSREG: NODE ADDRESS SET REGISTER (ADDRESS:0x1D) (POR:0x00)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
NLADDR<7:0>
PLDPLEN<6:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
© 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
bit 0