XRT75R12DIB-F Exar Corporation, XRT75R12DIB-F Datasheet - Page 112

• Manufacturer Part Number: XRT75R12DIB-F
• Description: Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
• Manufacturer: Exar Corporation

Specifications of XRT75R12DIB-F

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V to 5 V
• Package / Case: TBGA-420
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
In this application, these Mapper devices can be thought of as multi-channel devices. For example, an STS-3
Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, an STS-12 Mapper can be
viewed as a 12-Channel DS3/STS-1 to STS-12 Mapper IC. Continuing on with this line of thought, if a Mapper
IC is configured to receive an STS-N signal, and (from this STS-N signal) de-map and output N DS3 signals
(towards the DS3 facility), then it will typically do so in the following manner.
Now, since the Mapper IC will output the entire STS-1 data stream (via the Data-Signal), the output Clock-
Signal will be of the form such that it has a period of 19.3ns (e.g., a 51.84MHz clock signal). However, the
Mapper IC will still generate approximately 44,736,000 clock pulses during any given one second period.
Hence, the clock signal that is output from the Mapper IC will be a horribly gapped 44.736MHz clock signal.
One can view such a clock signal as being a very-jittery 44.736MHz clock signal. This jitter that exists within
the "Clock-Signal" is referred to as "Clock-Gapping" Jitter. A more detailed discussion on how the user must
handle this type of jitter is presented in
Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit
Inputs of the LIU” on page
The "Category I Intrinsic Jitter Requirements" per Telcordia GR-253-CORE (for DS3 applications) mandates
that the user perform a large series of tests against certain specified "Scenarios". These "Scenarios" and their
corresponding requirements is summarized in
T
8.5
ABLE
In many cases, the Mapper IC will output this DS3 signal, using both a "Data-Signal" and a "Clock-Signal".
In many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data-Signal.
However, as the Mapper IC output this STS-1 data-stream, it will typically supply clock pulses (via the Clock-
Signal output) coincident to whenever a DS3 bit is being output via the Data-Signal. In this case, the Mapper
IC will NOT supply a clock pulse coincident to when a TOH, POH, or any "non-DS3 data-bit" is being output
via the "Data-Signal".
Phase Transients
DS3 De-Mapping
Single Pointer
Pointer Bursts
D
87-3 Pattern
87-3 Cancel
Adjustment
S
ESCRIPTION
87-3 Add
43: S
CENARIO
Jitter
A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3
applications
UMMARY OF
S
N
CENARIO
UMBER
"C
A1
A2
A3
A4
A5
A5
ATEGORY
119.
T
ELCORDIA
J
C
I I
ITTER
ATEGORY
NTRINSIC
0.3UI-pp + Ao
“Section 8.8.2, Recommendations on Pre-Processing the Gapped
0.4UI-pp
1.3UI-pp
1.2UI-pp
1.0UI-pp
1.3UI-pp
1.3UI-pp
R
EQUIREMENTS
GR-253-CORE
I I
Table
J
NTRINSIC
APPLICATIONS
ITTER
43, below.
108
R
EQUIREMENT PER
Includes effects of De-Mapping and Clock Gapping Jit-
ter
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.NOTE: Ao is the amount
of intrinsic jitter that was measured during the "DS3 De-
Mapping Jitter" phase of the Test.
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
T
ELCORDIA
C
OMMENTS
GR-253-CORE,
REV. 1.0.3
FOR
DS3