XRT75R12DIB-F Exar Corporation, XRT75R12DIB-F Datasheet - Page 23

• Manufacturer Part Number: XRT75R12DIB-F
• Description: Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
• Manufacturer: Exar Corporation

Specifications of XRT75R12DIB-F

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V to 5 V
• Package / Case: TBGA-420
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.3
The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks
used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS-
3 or SFM clock input. Therefore, if the chip is configured for STS-1 only or E3 only, then the DS-3 input pin
must be connected to the STS-1 pin or E3 pin respectively. In DS-3 mode or when SFM is used, the STS-1
and E3 input pins can be left unconnected. If SFM is enabled by pulling the SFM_EN pin "High", 12.288MHz is
the only clock reference necessary to generate DS-3, E3, or STS-1 line rates and the microprocessor timing.
A simplified block diagram of the clock synthesizer is shown in
specifications can be found on
N
F
2.0 CLOCK SYNTHESIZER
t
t
OTES
IGURE
RISE_REFCLK
FALL_REFCLK
REF
REF
REF
S
REF
CLK
REF
1. Required to meet Bellcore GR-499 specification on frequency stability requirements. However, the LIU can
2. Reference clock jitter limits are required for the transmit output to meet ITU-T and Bellcore system level jitter
YMBOL
:
DUTY
STS1
SFM
DS3
JIT
3. S
E3
functionally operate with ±100 ppm without meeting the required specifications.
requirements.
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
IMPLIFIED
Reference Clock Duty Cycle
E3 Reference Clock Frequency Tolerance
DS3 Reference Clock Frequency Tolerance
STS-1 Reference Clock Frequency Tolerance
SFM Reference Clock Frequency Tolerance
Reference Clock Rise Time (10% to 90%)
Reference Clock Fall Time (90% to 10%)
Reference Clock Jitter Stability
SFM_EN
B
LOCK
STS-1Clk/12M
T
ABLE
D
Table 2
IAGRAM OF THE
2: R
P
ARAMETER
DS3Clk
EFERENCE
below.
2
E3Clk
0
1
I
C
NPUT
LOCK
1
C
1
1
19
P
LOCK
1
ERFORMANCE
Clock Synthesizer
Processor
C
IRCUITRY
M
-20
-20
-20
-20
40
Figure
IN
S
PECIFICATIONS
D
RIVING THE
3. Reference clock performance
T
YP
M
ICROPROCESSOR
CLKOUT_n
LOL_n
0.005
M
+20
+20
+20
+20
60
5
5
AX
XRT75R12D
U
UI
ppm
ppm
ppm
ppm
NITS
ns
ns
%
p2p