LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 214

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-58. PFU Based Distributed Dual Port RAM Timing Waveform – With Output Registers
Distributed ROM (Distributed_ROM) – PFU Based
PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These
LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-59 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 9-59. Distributed ROM Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. The basic Distributed Dual Port RAM
primitive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-60.
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClock
RdClock
Reset
Data
WE
Q
t
t
t
SUWREN_PFU
SUWREN_PFU
t
SUADDR_PFU
SUDATA_PFU
Data_0
Add_0
OutClockEn
OutClock
t
t
HADDR_PFU
HDATA_PFU
Address
t
HWREN_PFU
Reset
Invalid Data
Data_1
Add_1
9-49
Distributed ROM
PFU-based
t
SUCE_PFU
Add_0
LatticeECP/EC and LatticeXP Devices
t
HWREN_PFU
t
CORAM_PFU
Q
Data_0
Add_1
Memory Usage Guide
Data_1
t
HCE_PFU