LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 5

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Memory Usage Guide for LatticeECP/EC and LatticeXP Devices
LatticeECP/EC and LatticeXP DDR Usage Guide
Introduction ........................................................................................................................................................ 9-1
Memories in LatticeECP/EC and LatticeXP Devices ......................................................................................... 9-1
Utilizing IPexpress.............................................................................................................................................. 9-3
Memory Modules................................................................................................................................................ 9-7
Initializing Memory ........................................................................................................................................... 9-51
Technical Support Assistance.......................................................................................................................... 9-53
Revision History ............................................................................................................................................... 9-53
Appendix A. Attribute Definitions...................................................................................................................... 9-54
Introduction ...................................................................................................................................................... 10-1
DDR SDRAM Interfaces Overview................................................................................................................... 10-1
Implementing DDR Memory Interfaces with the LatticeECP/EC Devices........................................................ 10-2
Generic High Speed DDR Implementation .................................................................................................... 10-17
Board Design Guidelines ............................................................................................................................... 10-17
References..................................................................................................................................................... 10-18
Technical Support Assistance........................................................................................................................ 10-18
Revision History ............................................................................................................................................. 10-18
Appendix A. Using IPexpress™ to Generate DDR Modules.......................................................................... 10-19
Appendix B. Verilog Example for DDR Input and Output Modules ................................................................ 10-21
Appendix C. VHDL Example for DDR Input and Output Modules.................................................................. 10-24
Appendix D. Generic (Non-Memory) High-Speed DDR Interface .................................................................. 10-29
Appendix E. List of Compatible DDR SDRAM ............................................................................................... 10-33
Appendix F. DDR400 Interface using the LatticeEC Evaluation Board.......................................................... 10-36
IPexpress Flow.......................................................................................................................................... 9-3
Single Port RAM (RAM_DQ) – EBR Based .............................................................................................. 9-7
True Dual Port RAM (RAM_DP_TRUE) – EBR Based ........................................................................... 9-13
Pseudo Dual Port RAM (RAM_DP) – EBR-Based.................................................................................. 9-22
Read Only Memory (ROM) – EBR Based............................................................................................... 9-25
First In First Out (FIFO, FIFO_DC) – EBR Based................................................................................... 9-28
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based.......................................................... 9-44
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based ............................................................ 9-46
Distributed ROM (Distributed_ROM) – PFU Based ................................................................................ 9-49
Initialization File Format .......................................................................................................................... 9-51
DATA_WIDTH......................................................................................................................................... 9-54
REGMODE.............................................................................................................................................. 9-54
RESETMODE ......................................................................................................................................... 9-54
CSDECODE............................................................................................................................................ 9-54
WRITEMODE.......................................................................................................................................... 9-54
GSR ........................................................................................................................................................ 9-54
DQS Grouping......................................................................................................................................... 10-2
DDR Software Primitives......................................................................................................................... 10-5
Memory Read Implementation ................................................................................................................ 10-9
Data Read Critical Path......................................................................................................................... 10-12
DQS Postamble .................................................................................................................................... 10-13
Memory Write Implementation .............................................................................................................. 10-14
Design Rules/Guidelines....................................................................................................................... 10-16
QDR II Interface .................................................................................................................................... 10-17
FCRAM (Fast Cycle Random Access Memory) Interface..................................................................... 10-17
DDR Generic......................................................................................................................................... 10-19
DDR Memory Interface ......................................................................................................................... 10-20
VHDL Implementation ........................................................................................................................... 10-29
Verilog Example .................................................................................................................................... 10-31
Preference File...................................................................................................................................... 10-32
4
LatticeXP Family Handbook
Table of Contents