NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet - Page 316

• Manufacturer Part Number: NUMICRO-SDK
• Description: KIT EVAUATION NUC100/120/130/140
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r
• Type: MCUr

Specifications of NUMICRO-SDK

• Contents: Board, Cable, CD, Nu-Link
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NUC100, NUC120, NUC130, NUC140

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NuMicro™ NUC100 Series Technical Reference Manual
CFL_IE3
CRL_IE3
INV3
Reserved
CFLRI2
CRLRI2
Reserved
CAPIF2
CAPCH2EN
CFL_IE2
and CFLR (Falling latch).
When Disable, Capture does not update CRLR and CFLR, and disable PWM group
channel 3 Interrupt.
Channel 3 Falling Latch Interrupt Enable
1 = Enable falling latch interrupt
0 = Disable falling latch interrupt
When Enable, if Capture detects PWM group channel 3 has falling transition, Capture
issues an Interrupt.
Channel 3 Rising Latch Interrupt Enable
1 = Enable rising latch interrupt
0 = Disable rising latch interrupt
When Enable, if Capture detects PWM group channel 3 has rising transition, Capture
issues an Interrupt.
Channel 3 Inverter Enable
1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer
0 = Inverter disable
Reserved
CFLR2 Latched Indicator Bit
When PWM group input channel 2 has a falling transition, CFLR2 was latched with the
value of PWM down-counter and this bit is set by hardware.
In Medium Density, software can write 0 to clear this bit to zero.
In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can
Write 1 to clear this bit to zero if BCn bit is 1.
CRLR2 Latched Indicator Bit
When PWM group input channel 2 has a rising transition, CRLR2 was latched with the
value of PWM down-counter and this bit is set by hardware.
In Medium Density, software can write 0 to clear this bit to zero.
In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can
Write 1 to clear this bit to zero if BCn bit is 1.
Reserved
Channel 2 Capture Interrupt Indication Flag
If PWM group channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising
transition occurs at PWM group channel 2 will result in CAPIF2 to high; Similarly, a
falling transition will cause CAPIF2 to be set high if PWM group channel 2 falling latch
interrupt is enabled (CFL_IE2=1).
Write 1 to clear this bit to zero
Channel 2 Capture Function Enable
1 = Enable capture function on PWM group channel 2
0 = Disable capture function on PWM group channel 2
When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising
latch) and CFLR (Falling latch).
When Disable, Capture does not update CRLR and CFLR, and disable PWM group
channel 2 Interrupt.
Channel 2 Falling Latch Interrupt Enable
1 = Enable falling latch interrupt
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Publication Release Date: Dec. 22, 2010
Revision V1.06