NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet - Page 473
![KIT EVAUATION NUC100/120/130/140](/photos/18/31/183177/numicro-sdk_sml.jpg)
NUMICRO-SDK
Manufacturer Part Number
NUMICRO-SDK
Description
KIT EVAUATION NUC100/120/130/140
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Type
MCUr
Datasheets
1.NUC100LC1BN.pdf
(600 pages)
2.NUMICRO-SDK.pdf
(13 pages)
3.NUMICRO-SDK.pdf
(93 pages)
4.NUMICRO-SDK.pdf
(1 pages)
Specifications of NUMICRO-SDK
Contents
Board, Cable, CD, Nu-Link
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
NUC100, NUC120, NUC130, NUC140
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUMICRO-SDK
Manufacturer:
Nuvoton Technology Corporation
Quantity:
135
Company:
Part Number:
NUMICRO-SDK
Manufacturer:
NuvoTon
Quantity:
69
- NUC100LC1BN PDF datasheet
- NUMICRO-SDK PDF datasheet #2
- NUMICRO-SDK PDF datasheet #3
- NUMICRO-SDK PDF datasheet #4
- Current page: 473 of 600
- Download datasheet (6Mb)
5.15.6 Register Description
I
Register
I2S_CON
Bits
[31:22]
[21]
[20]
[19]
[18]
2
S Control Register (I2S_CON)
Reserved
MCLKEN
FORMAT
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
I2S_BA+0x00
Descriptions
Reserved
RXDMA
TXDMA
CLR_RXFIFO
CLR_TXFIFO
Reserved
MONO
30
22
14
6
RXTH[2:0]
RXDMA
R/W
R/W
Reserved
Enable Receive DMA
When RX DMA is enabled, I
SRAM if FIFO is not empty.
1 = Enable RX DMA
0 = Disable RX DMA
Enable Transmit DMA
When TX DMA is enables, I
FIFO if FIFO is not full.
1 = Enable TX DMA
0 = Disable TX DMA
Clear Receive FIFO
Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and
RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty.
This bit is cleared by hardware automatically, read it return zero.
Clear Transmit FIFO
Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and
TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in
transmit FIFO is not changed.
This bit is clear by hardware automatically, read it return zero.
29
21
13
5
WORDWIDTH
Description
I
2
S Control Register
TXDMA
28
20
12
4
- 473 -
Reserved
CLR_RXFIFO CLR_TXFIFO
2
2
S request DMA to transfer data from SRAM to transmit
MUTE
S requests DMA to transfer data from receive FIFO to
27
19
11
3
Publication Release Date: Oct 22, 2010
TXTH[2:0]
RXEN
26
18
10
2
LCHZCEN
TXEN
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
RCHZCEN
SLAVE
I2SEN
24
16
8
0
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