NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet - Page 345

• Manufacturer Part Number: NUMICRO-SDK
• Description: KIT EVAUATION NUC100/120/130/140
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r
• Type: MCUr

Specifications of NUMICRO-SDK

• Contents: Board, Cable, CD, Nu-Link
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NUC100, NUC120, NUC130, NUC140

Variable Serial Clock Frequency
In master mode, the output of serial clock can be programmed as variable frequency pattern if the
Variable Clock Enable bit VARCLK_EN (SPI_CNTRL[23]) is enabled. The frequency pattern
format is defined in VARCLK (SPI_VARCLK[31:0]) register. If the bit content of VARCLK is ‘0’ the
output frequency is according with the DIVIDER (SPI_DIVIDER[15:0]) and if the bit content of
VARCLK is ‘1’, the output frequency is according to the DIVIDER2 (SPI_DIVIDER[31:16]). Figure
5-52 is the timing relationship among the serial clock (SPICLK), the VARCLK, the DIVIDER and
the DIVIDER2 registers. A two-bit combination in the VARCLK defines one clock cycle. The bit
field VARCLK[31:30] defines the first clock cycle of SPICLK. The bit field VARCLK[29:28] defines
the second clock cycle of SPICLK and so on. The clock source selections are defined in VARCLK
and it must be set 1 cycle before the next clock option. For example, if there are 5 CLK1 cycle in
SPICLK, the VARCLK shall set 9 ‘0’ in the MSB of VARCLK. The 10th shall be set as ‘1’ in order
to switch the next clock source is CLK2. Note that when enable the VARCLK_EN bit, the setting
of TX_BIT_LEN must be programmed as 0x10 (16 bits mode only).
Clock Polarity
The CLKP bit (SPI_CTL[11]) defines the serial clock idle state in master mode only. If CLKP = 1,
the output SPICLK is idle at high state, otherwise it is at low state if CLKP = 0. For variable serial
clock, it works in CLKP = 0 only.
Transmit/Receive Bit Length
The bit length of a transaction word is defined in TX_BIT_LEN bit field (SPI_CNTRL[7:3]). It can
be configured up to 32 bits length in a transaction word for transmitting and receiving.
(DIVIDER2)
(DIVIDER)
VARCLK
SPICLK
NuMicro™ NUC100 Series Technical Reference Manual
CLK1
CLK2
Figure 5-52 Variable Serial Clock Frequency
Figure 5-53 32-Bit in one Transaction
00000000011111111111111110000111
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Publication Release Date: Oct 22, 2010
Revision V1.06