PIC32MX695F512L-80I/BG Microchip Technology, PIC32MX695F512L-80I/BG Datasheet - Page 119

IC, 32BIT MCU, PIC32, 80MHZ, BGA-100

PIC32MX695F512L-80I/BG

Manufacturer Part Number
PIC32MX695F512L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX695F512L-80I/BG

Controller Family/series
PIC32
Ram Memory Size
128KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
512 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX6xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
PIC32MX695F512L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
PIC32MX695F512L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
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11.0
The Universal Serial Bus (USB) module contains ana-
log and digital components to provide a USB 2.0 full-
speed and low-speed embedded host, full-speed
device, or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA control-
ler, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32MX USB OTG
module is presented in Figure 11-1.
 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
USB ON-THE-GO (OTG)
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “USB On-
The-Go
“PIC32MX Family Reference Manual” ,
which is available from the Microchip web
site (www.microchip.com/PIC32).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
(OTG)”
(DS61126)
in
the
Preliminary
PIC32MX5XX/6XX/7XX
The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communi-
cation. The voltage comparators monitor the voltage on
the V
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers, and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The inte-
grated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface
communicate with the module.
The PIC32MX USB module includes the following
features:
• USB Full-Speed Support for Host and Device
• Low-Speed Host Support
• USB OTG Support
• Integrated Signaling Resistors
• Integrated Analog Comparators for V
• Integrated USB Transceiver
• Transaction Handshaking Performed by
• Endpoint Buffering Anywhere in System RAM
• Integrated DMA to Access System RAM and
Monitoring
Hardware
Flash
Note:
BUS
pin to determine the state of the bus. The
allows
IMPORTANT! The implementation and
use of the USB specifications, as well as
other third-party specifications or technol-
ogies, may require licensing; including,
but not limited to, USB Implementers
Forum, Inc. (also referred to as USB-IF).
The user is fully responsible for investigat-
ing and satisfying any applicable licensing
obligations.
the
CPU
to
DS61156B-page 119
configure
BUS
and

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