PIC32MX695F512L-80I/BG Microchip Technology, PIC32MX695F512L-80I/BG Datasheet - Page 162

• Manufacturer Part Number: PIC32MX695F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX695F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX6xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX5XX/6XX/7XX
28.2
This section describes the operation of the WDT and
Power-Up Timer of the PIC32MX5XX/6XX/7XX.
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by reset-
ting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
The following are some of the key features of the WDT
module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
FIGURE 28-1:
DS61156B-page 162
WDTCLR = 1
WDT Enable
WDT Enable
Reset Event
Watchdog Timer (WDT)
PWRT Enable
Oscillator
WDT Enable
LPRC
Wake
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
WDT Counter Reset
Clock
Preliminary
25-bit Counter
FWDTPS<4:0>(DEVCFG1<20:16>)
1:64 Output
25
1
Decoder
PWRT Enable
Power Save
 2009 Microchip Technology Inc.
0
1
Control
PWRT
LPRC
Device Reset
NMI (Wake-up)