PIC32MX695F512L-80I/BG Microchip Technology, PIC32MX695F512L-80I/BG Datasheet - Page 133

• Manufacturer Part Number: PIC32MX695F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX695F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX6xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.0
 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
INTER-INTEGRATED CIRCUIT
(I
2
C™)
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “Inter-Inte-
grated
“PIC32MX Family Reference Manual” ,
which is available from the Microchip web
site (www.microchip.com/PIC32).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Circuit”
(DS61116)
in
the
Preliminary
PIC32MX5XX/6XX/7XX
The I
for both Slave and Multi-Master modes of the I
communication standard. Figure 18-1 shows the I
module block diagram.
Each I
clock and the SDAx pin is data.
Each I
• I
• I
• I
• I
• Serial Clock Synchronization for I
• I
• Provides Support for Address Bit Masking
Operation
Master and Slaves
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
Collision and Arbitrates Accordingly
2
2
2
2
2
C Interface Supporting both Master and Slave
C Slave mode Supports 7 and 10-bit Address
C Master mode Supports 7 and 10-bit Address
C Port allows Bidirectional Transfers between
C Supports Multi-master Operation; Detects Bus
2
C module provides complete hardware support
2
2
C module has a 2-pin interface: the SCLx pin is
C module offers the following key features:
DS61156B-page 133
2
C Port can be
2
C serial
2
C