PIC32MX695F512L-80I/BG Microchip Technology, PIC32MX695F512L-80I/BG Datasheet - Page 190

• Manufacturer Part Number: PIC32MX695F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX695F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX6xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX5XX/6XX/7XX
FIGURE 31-4:
DS61156B-page 190
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Internal Voltage Regulator Enabled
External V
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and S
Note 1: The power-up period will be extended if the power-up sequence completes before the device
DDCORE
2: Includes interval voltage regulator stabilization delay.
3: Power-Up Timer (PWRT); only active when the internal voltage regulator is disabled.
Power-up Sequence
(Note 2)
Power-up Sequence
(Note 2)
(Note 3)
Power-up Sequence
exits from BOR (V
Provided
POWER-ON RESET TIMING CHARACTERISTICS
V
V
POR
POR
V
POR
DD
(Note 1)
(Note 1)
< V
(T
SY00
(T
SY00
PU
PU
DDMIN
)
)
(T
(T
(Note 1)
SY01
SYSDLY
SY02
PWRT
).
Preliminary
(T
SY10
OSC
)
OST
)
(T
SYSDLY
SY02
)
)
(T
CPU starts fetching code
SYSDLY
SY02
)
)
CPU starts fetching code
V
V
DD
DDCORE
CPU starts fetching code
V
V
DD
DD
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