PIC32MX695F512L-80I/BG Microchip Technology, PIC32MX695F512L-80I/BG Datasheet - Page 123

• Manufacturer Part Number: PIC32MX695F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX695F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX6xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.0
FIGURE 13-1:
 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features of
SOSCO/T1CK
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
2: Some registers and associated bits
SOSCI
TIMER1
T1IF
Event Flag
Configuration Word DEVCFG1.
the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS61105) in the “PIC32MX Family
Reference Manual” , which is available
from
(www.microchip.com/PIC32).
described in this section may not be avail-
able
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
on
the
TGATE (T1CON<7>)
TIMER1 BLOCK DIAGRAM
0
1
all
Microchip
Reset
devices.
Equal
SOSCEN
16-bit Comparator
web
Refer
TMR1
PR1
site
Preliminary
PBCLK
to
Q
Q
(1)
Gate
Sync
D
PIC32MX5XX/6XX/7XX
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can oper-
ate as a free-running interval timer for various timing
applications and counting external events. This timer
can also be used with the Low-Power Secondary
Oscillator (S
following modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
13.1
• Selectable Clock Prescaler
• Timer Operation during CPU Idle and Sleep mode
• Fast Bit Manipulation using CLR, SET and INV
• Asynchronous mode can be used with the S
Registers
to function as a Real-Time Clock (RTC).
Additional Supported Features
1 0
x 1
0 0
OSC
) for real-time clock applications. The
TSYNC (T1CON<2>)
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
0
1
1, 8, 64, 256
(T1CON<5:4>)
Prescaler
TCKPS<1:0>
Sync
DS61156B-page 123
2
OSC