PIC32MX695F512L-80I/BG Microchip Technology, PIC32MX695F512L-80I/BG Datasheet - Page 169

• Manufacturer Part Number: PIC32MX695F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX695F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX6xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 29-1:
 2009 Microchip Technology Inc.
INS
J
JAL
JALR
JALR.HB
JR
JR.HB
LB
LBU
LH
LHU
LL
LUI
LW
LWPC
LWL
LWR
MADD
MADDU
MFC0
MFHI
MFLO
MOVN
MOVZ
MSUB
MSUBU
MTC0
MTHI
MTLO
MUL
MULT
MULTU
NOP
Note 1:
Instruction
This instruction is deprecated and should not be used.
Insert Bit Field
Unconditional Jump
Jump and Link
Jump and Link Register
Jump and Link Register with Hazard Barrier
Jump Register
Jump Register with Hazard Barrier
Load Byte
Unsigned Load Byte
Load Halfword
Unsigned Load Halfword
Load Linked Word
Load Upper Immediate
Load Word
Load Word, PC relative
Load Word Left
Load Word Right
Multiply-Add
Multiply-Add Unsigned
Move From Co-processor 0
Move From HI
Move From LO
Move Conditional on Not Zero
Move Conditional on Zero
Multiply-Subtract
Multiply-Subtract Unsigned
Move To Co-processor 0
Move To HI
Move To LO
Multiply with register write
Integer Multiply
Unsigned Multiply
No Operation (Assembler idiom for: SLL r0, r0, r0)
MIPS32
®
INSTRUCTION SET (CONTINUED)
Description
Preliminary
PIC32MX5XX/6XX/7XX
Rt = InsertField(Rs, Rt, pos,
size)
PC = PC[31:28] || offset<<2
GPR[31] = PC + 8
PC = PC[31:28] || offset<<2
Rd = PC + 8
PC = Rs
Like JALR , but also clears execution and
instruction hazards
PC = Rs
Like JR , but also clears execution and
instruction hazards
Rt = (byte)Mem[Rs+offset]
Rt = (ubyte))Mem[Rs+offset]
Rt = (half)Mem[Rs+offset]
Rt = (uhalf)Mem[Rs+offset]
Rt = Mem[Rs+offset]
LLbit = 1
LLAdr = Rs + offset
Rt = immediate << 16
Rt = Mem[Rs+offset]
Rt = Mem[PC+offset]
Rt = Rt Merge Mem[Rs+offset]
Rt = Rt Merge Mem[Rs+offset]
HI | LO += (int)Rs * (int)Rt
HI | LO += (uns)Rs * (uns)Rt
Rt = CPR[0, Rd, sel]
Rd = HI
Rd = LO
if Rt ¼ 0 then
if Rt = 0 then
HI | LO -= (int)Rs * (int)Rt
HI | LO -= (uns)Rs * (uns)Rt
CPR[0, n, Sel] = Rt
HI = Rs
LO = Rs
HI | LO =Unpredictable
Rd = ((int)Rs * (int)Rt)
HI | LO = (int)Rs * (int)Rd
HI | LO = (uns)Rs * (uns)Rd
Rd = Rs
Rd = Rs
Function
DS61156B-page 169
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