MT9V011P11STC:B Aptina LLC, MT9V011P11STC:B Datasheet - Page 17

• Manufacturer Part Number: MT9V011P11STC:B
• Description: SENSOR IMAGE VGA COLOR CMOS PLCC
• Manufacturer: Aptina LLC
• Series: DigitalClarity®, Micron®r
• Type: CMOS Imagingr

Specifications of MT9V011P11STC:B

• Pixel Size: 5.6µm x 5.6µm
• Active Pixel Array: 640H x 480V
• Frames Per Second: 30
• Voltage - Supply: 2.8V
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1315

Register Descriptions
Table 7:
PDF: 817d5189/Source: 817d5173
MT9V011_C82S_2_PLCC.fm - Rev. B 1/05 EN
Register
0x00 / 0xFF
Chip Version
Window Control
These registers control the size of the window.
Blanking Control
These registers control the blanking time in a row and between frames.
Output Control
This register controls various features of the output format for the sensor.
0x01
0x02
0x03
0x04
0x05
0x06
0x07
8 -11
Register Description
0-15
0-11
Bit
0-8
0-9
0-8
0-9
0-9
15
0
1
4
5
6
This register is read-only and gives the chip identification number: 0x8243.
First row to be read out
Minimum recommended value = 0x0006.
First column to be read out
Window height (number of rows - 1)
Window width (number of columns - 1)
Minimum recommended value = 0x0009.
Horizontal Blanking (number of columns)
Minimum value for 0x05 = 0x0009.
Minimum recommended value for 0x05 = 0x007B (123 pixel clocks).
Vertical Blanking (number of rows -1)
Minimum recommended value = 0x0003.
Synchronize changes (copied to Reg0xF1, bit1).
0 = normal operation, update changes to registers that affect image brightness (integration time,
integration delay, gain, horizontal and vertical blanking, window size, row/column skip, or row
mirror) at the next frame boundary.
1 = do not update any changes to these settings until this bit is returned to “0.”
Chip Enable (copied to Reg0xF1, bit0).
1 = normal operation.
0 = stop sensor readout. When this is returned to “1,” sensor readout restarts at the starting row in a
new frame. The digital power consumption can then also be reduced to less than 5uA by turning off
the master clock.
By setting this bit to “1,” the sampling and reset timing of the pixels will be halved. This bit should
therefore only be used if the master clock frequency is 13.5 MHz or less. When this bit is set the
minimum recommended horizontal blanking value is 17, compared to 123 when this bit is not set.
Shutter Delay will be master clocks divided by 2 when this bit is set, compared to master clocks
divided by 4 when this bit is 0.
Note: Use this register for 15 fps with 12 MHz master clock.
Allow Shutter Width to be exactly one full frame.
0 = normal operation = Maximum Shutter Width equals the total number of rows - 1. If Shutter
Width exceeds the number of rows -1, the total number of rows in the image will be increased to
Shutter Width + 1.
1 = Maximum Shutter Width equals the total number of rows. When the Shutter Width exceeds the
number of rows, the total number of rows in the image will be increased to match the Shutter Width.
Reserved.
0 = normal operation.
Shift pixel clock: (11,10,9,8) = (1, x, x, x): shift pixel clock 1 clock earlier (0, 1, x, x): shift pixel clock ½
clock earlier (0, 0, 1, x): delay pixel clock by ½ clock(0, 0, 0, 1): delay pixel clock by 1 clock (0, 0, 0, 0):
no delay pixel clock (default mode).
Invert pixel clock:
0 = normal operation.
1 = invert pixel clock.
—
default = 0x000A (10).
—
default = 0x0016 (22). Minimum recommended value = 0x0012 (18).
—
—
MT9V011 - 1/4-Inch VGA Digital Image Sensor
17
default = 0x01DF (479).
—
default = 0x001C (28 rows).
—
default = 0x027F (639).
default = 0x0083 (131 pixel clocks).
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Preliminary
Registers
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