MT9V011P11STC:B Aptina LLC, MT9V011P11STC:B Datasheet - Page 20

• Manufacturer Part Number: MT9V011P11STC:B
• Description: SENSOR IMAGE VGA COLOR CMOS PLCC
• Manufacturer: Aptina LLC
• Series: DigitalClarity®, Micron®r
• Type: CMOS Imagingr

Specifications of MT9V011P11STC:B

• Pixel Size: 5.6µm x 5.6µm
• Active Pixel Array: 640H x 480V
• Frames Per Second: 30
• Voltage - Supply: 2.8V
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1315

Feature Description
Window Control
Blanking Control
Table 8:
Pixel Integration Control
PDF: 817d5189/Source: 817d5173
MT9V011_C82S_2_PLCC.fm - Rev. B 1/05 EN
Reg0x06
1-2
3+
0
Vertical Blanking
Reg0x01 Row Start, Reg0x02 Column Start, Reg0x03 Window Height (row size), and
Reg0x04 Window Width (column size)
These registers control the size and starting coordinates of the window. By changing
these registers, any image format smaller than or equal to VGA can be specified.
Reg0x05 Horizontal Blanking, and Reg0x06 Vertical Blanking
Blanking Control:
These registers control the blanking time in a row (called column fill-in or horizontal
blanking) and between frames (vertical blanking).
• Horizontal blanking is specified in terms of pixel clocks.
• Vertical blanking is specified in terms of row readout times. (The programmed value
The actual imager timing can be calculated using Table 3 on page 10 which describes
"Row Timing and FRAME_VALID/LINE_VALID Signals.”
The number of dark rows read out depends on the vertical blanking set as shown in the
Table 8.
Reg0x09 Shutter Width, and Reg0x0C Shutter Delay
These registers (along with the Window Size and horizontal blanking registers) control
the integration time for the pixels.
The actual total integration time,
t
If the value in Reg0x0C exceeds (row time - 444)/K master clock cycles, the row time will
be extended by (K x Reg0x0C - (row time - 444)) clock cycles.
Where :
K = 4 when Reg0x07[4] = 0, and
INT =
is one less than the actual value.)
Reg0x09: number of rows of integration, default = 0x01FC (508)
Reg0x0C: reset delay, default = 0x0000 (0). This is the number of master clocks that the
timing and control logic waits before asserting the reset for a given row.
Reg0x09 x Row Time - Overhead time - Reset delay, where:
Row Time = (Reg0x04 + 1 + 113 + Reg0x05) x (Reg0x0A + 2) master clock periods
Overhead time = K x 57 master clock periods
Reset delay = K x Reg0x0C master clock periods
# Dark Rows
0
2
4
MT9V011 - 1/4-Inch VGA Digital Image Sensor
20
t
INT, is:
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Feature Description
Preliminary
‡