MT9V011P11STC:B Aptina LLC, MT9V011P11STC:B Datasheet - Page 9

• Manufacturer Part Number: MT9V011P11STC:B
• Description: SENSOR IMAGE VGA COLOR CMOS PLCC
• Manufacturer: Aptina LLC
• Series: DigitalClarity®, Micron®r
• Type: CMOS Imagingr

Specifications of MT9V011P11STC:B

• Pixel Size: 5.6µm x 5.6µm
• Active Pixel Array: 640H x 480V
• Frames Per Second: 30
• Voltage - Supply: 2.8V
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1315

Figure 6: Spatial Illustration of Image Readout
Output Data Timing
Figure 7: Timing Example of Pixel Data
Figure 8: Row Timing and FRAME_VALID/LINE_VALID Signals
PDF: 817d5189/Source: 817d5173
MT9V011_C82S_2_PLCC.fm - Rev. B 1/05 EN
D
OUT9
The data output of the MT9V011 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
LINE_VALID
The rising edges of the PIXCLK signal are nominally timed to occur one-half of a master
clock period after the D
data. The PIXCLK is HIGH for one complete master clock period and then LOW for one
complete master clock period. It is continuously enabled, even during the blanking
period. The MT9V011 can be programmed to move the PIXCLK edge relative to the
D
can be achieved by programming the corresponding bits in Reg0x07.
The parameters P, A, and Q in Figure 8 are defined in Table 3.
Number of master clocks
P
FRAME_VALID
OUT
-D
m-1,0
PIXCLK
P
P
P
0,0
1,0
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
LINE_VALID
OUT0
m,0
P
P
P
0,1
1,1
m-1,1
P
m,1
transitions from +1 to -1 master clock, in steps of one-half of a master clock. This
P
P
0,2
1,2
.....................................P
.....................................P
VERTICAL BLANKING
.....................................P
.....................................P
VALID IMAGE
Blanking
(9:0)
P
P 0
m-1,n-1
m,n-1
0,n-1
1,n-1
P
OUT
m,n
A
P
P
P
0,n
1,n
m-1,n
(9:0)
P 1
edges. This allows PIXCLK to be used as a clock to latch the
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
MT9V011 - 1/4-Inch VGA Digital Image Sensor
Q
VERTICAL/HORIZONTAL
9
HORIZONTAL
(9:0)
BLANKING
BLANKING
Valid Image Data
P2
. . .
. . .
. . .
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(9:0)
P 3
A
(9:0)
P 4
Q
. . . .
. . . .
. . . .
. . . .
A
P n-1
(9:0)
P
(9:0)
P n
©2004 Micron Technology, Inc. All rights reserved.
Pixel Data Format
Blanking
Preliminary
‡