PN5120A0HN1/C1 NXP Semiconductors, PN5120A0HN1/C1 Datasheet - Page 89

• Manufacturer Part Number: PN5120A0HN1/C1
• Description: RF Wireless Misc COMBO ANALOG/DIGI IC
• Manufacturer: NXP Semiconductors
• Type: Transmission Moduler

Specifications of PN5120A0HN1/C1

• Package / Case: HVQFN EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PN5120A0HN1/C1,157

NXP Semiconductors
12. FIFO-buffer
111334
Product data sheet
12.2.1 Access rules
12.1 Overview
12.2 Accessing the FIFO-buffer
12.3 Controlling the FIFO-buffer
An 64*8-bit FIFO-buffer is implemented in the PN512. It buffers the input and output data
stream between the host controller and the internal state machine of the PN512. Thus, it
is possible to handle data streams with lengths of up to 64 bytes without taking timing
constraints into account.
The
Writing to this register stores one byte in the FIFO-buffer and increments the internal
FIFO-buffer write-pointer. Reading from this register shows the FIFO-buffer contents
stored at the FIFO-buffer read-pointer and decrements the FIFO-buffer read-pointer. The
distance between the write- and read-pointer can be obtained by reading the register
FIFOLevelReg.
When the μ-Controller starts a command, the PN512 may, while the command is in
progress, access the FIFO-buffer according to that command. Physically only one
FIFO-buffer is implemented, which can be used in input- and output direction. Therefore
the μ-Controller has to take care, not to access the FIFO-buffer in an unintended way.
Besides writing to and reading from the FIFO-buffer, the FIFO-buffer pointers might be
reset by setting the bit FlushBuffer in the register FIFOLevelReg to 1. Consequently, the
FIFOLevel bits are set to logic 0 the bit BufferOvfl in the register ErrorReg is cleared, the
actually stored bytes are not accessible any more and the FIFO-buffer can be filled with
another 64 bytes again.
FIFO-buffer
input and output data bus is connected to the register FIFODataReg.
Rev. 3.4 — 8 September 2009
Transmission Module
© NXP B.V. 2010. All rights reserved.
PN512
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