PN5120A0HN1/C1 NXP Semiconductors, PN5120A0HN1/C1 Datasheet - Page 95

• Manufacturer Part Number: PN5120A0HN1/C1
• Description: RF Wireless Misc COMBO ANALOG/DIGI IC
• Manufacturer: NXP Semiconductors
• Type: Transmission Moduler

Specifications of PN5120A0HN1/C1

• Package / Case: HVQFN EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PN5120A0HN1/C1,157

NXP Semiconductors
16. Power reduction modes
111334
Product data sheet
16.1 Hard Power-down
16.2 Soft Power-down
16.3 Transmitter Power-down
A Hard Power-down is enabled with LOW level on pin NRSTPD. This turns off all internal
current sinks as well as the oscillator. All digital input buffers are separated from the input
pads and clamped internally (except pin NRSTPD itself). The output pins are frozen at a
certain value.
The RF level detector is not working.
The Soft Power-down mode is entered immediately after setting the bit Power-down in the
register CommandReg to 1. All internal current sinks are switched off (including the
oscillator buffer).
In opposition to the Hard Power-down mode, the digital input-buffers are not separated
from the input pads and keep their functionality. The digital output pins do not change their
state.
During Soft Power-down all registers values, the FIFO’s content and the configuration
itself will keep its content and the RF level detector is working.
If the bit AutoWakeUp in the register TxAutoReg is set and an external RF field is
detected, the Soft Power-down mode is left automatically.
After setting bit Power-down in the register CommandReg to 0 it takes 1024 clocks until
the Soft Power-down mode is left as indicated by the Power-down bit itself. Setting it to
logic 0 does not immediately clear it. It is cleared automatically by the PN512 when the
Soft Power-down mode is left.
Note: If the internal oscillator is used, you have to take into account that it is supplied by
AVDD and it will take a certain time t
can be detected by the internal logic.
Note: If the serial UART interface is used, then the PN512 recovers from soft Power-down
mode by sending the value 55 (hex) to the PN512. For further access to the registers the
oscillator must be stable. The first read or write access must be to address 0.
For the serial UART it is recommended to send the value 55 (hex) first and perform read
accesses to address 0 till the PN512 answers to the last read command with the register
content of address 0. This indicates that the PN512 is active for further operation.
This procedure also has to be performed, when the bit AutoWakeUp in the register
TxAutoReg is set and the PN512 detects an external RF field.
The Transmitter Power-down mode switches off the internal antenna drivers to turn off the
RF field by setting either Tx1RfEn or TX2RFEn in the register TXControlReg to 0. The
receiver is still switched on, so the PN512 can be accessed by a second NFC device as a
target.
Rev. 3.4 — 8 September 2009
osc
until the oscillator is stable and the clock cycles
Transmission Module
© NXP B.V. 2010. All rights reserved.
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