82P2288BB8 IDT, Integrated Device Technology Inc, 82P2288BB8 Datasheet - Page 147

• Manufacturer Part Number: 82P2288BB8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB8

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

T1/J1 Transmit Configuration 4 (026H, 126H, 226H, 326H, 426H, 526H, 626H, 726H)
WDAT[6:0]:
SAMP[3:0] bits (b3~0, T1/J1-025H,...).
T1/J1 Receive Jitter Attenuation Configuration (027H, 127H, 227H, 327H, 427H, 527H, 627H, 727H)
RJITT_TEST:
RJA_LIMT:
of the JA can be widened to track the short term input jitter, thereby avoiding data corruption. This bit selects whether the bandwidth is normal or
widened.
RJA_E:
RJA_DP[1:0]:
RJA_BW:
Programming Information
IDT82P2288
Bit Name
These bits contain the data to be stored in the pulse template RAM which is addressed by the UI[1:0] bits (b5~4, T1/J1-025H,...) and the
= 0: The real time interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, T1/J1-039H,...). That is, the
current interval between the read and write pointer of the FIFO will be written into the RJITT[6:0] bits (b6~0, T1/J1-039H,...).
= 1: The peak-peak interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, T1/J1-039H,...). That is, the
current interval is compared with the old one in the RJITT[6:0] bits (b6~0, T1/J1-039H,...) and the larger one will be indicated by the RJITT[6:0] bits
(b6~0, T1/J1-039H,...); otherwise, the value in the RJITT[6:0] bits (b6~0, T1/J1-039H,...) will not be changed.
When the read and write pointer of the FIFO are within 2/3/4 bits (corresponding to the FIFO depth) of overflowing or underflowing, the bandwidth
= 0: Normal bandwidth is selected.
= 1: Widen bandwidth is selected. In this case, the JA will not attenuate the input jitter until the read/write pointer’s position is outside the 2/3/4 bits
window.
= 0: Disable the Receive Jitter Attenuator.
= 1: Enable the Receive Jitter Attenuator.
These two bits select the Jitter Attenuation Depth.
= 00: The Jitter Attenuation Depth is 128-bit.
= 01: The Jitter Attenuation Depth is 64-bit.
= 10 / 11: The Jitter Attenuation Depth is 32-bit.
This bit select the Jitter Transfer Function Bandwidth.
= 0: 5 Hz.
= 1: 1.26 Hz.
Bit Name
Default
Bit No.
Default
Bit No.
Type
Type
Reserved
7
7
Reserved
WDAT6
R/W
6
0
6
WDAT5
RJITT_TEST
R/W
5
0
R/W
5
0
WDAT4
R/W
RJA_LIMT
4
0
R/W
147
4
0
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
WDAT3
R/W
3
0
RJA_E
R/W
3
0
WDAT2
RJA_DP1
R/W
2
0
R/W
2
0
WDAT1
RJA_DP0
R/W
1
0
R/W
1
0
March 04, 2009
RJA_BW
WDAT0
R/W
R/W
0
0
0
0