82P2288BB8 IDT, Integrated Device Technology Inc, 82P2288BB8 Datasheet - Page 88

• Manufacturer Part Number: 82P2288BB8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB8

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.18.2.4 Offset
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/
MTSDA(MTSDB)
MTSIGA(MTSIGB) pin are always per-timeslot aligned with the data on
the TSDn/MTSDA(MTSDB) pin.
different operating modes and the configuration of the offset.
0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the timeslot
offset can be configured from 0 to 127 timeslots (0 & 127 are included).
Table 44: Related Bit / Register In Chapter 3.18
Functional Description
IDT82P2288
Note:
* ID means Indirect Register in the Transmit Payload Control function block.
(T1/J1 only)
(T1/J1 only)
TSOFF[6:0]
BOFF[2:0]
FBITGAP
MAP[1:0]
TCOFAE
TSLVCK
Bit offset and timeslot offset are both supported in all the operating
Refer to Chapter 3.18.1.4 Offset for the base line without offset in
In Non-multiplexed mode, the timeslot offset can be configured from
TMODE
TCOFAI
MTSDA
FSTYP
FSINV
TMUX
PCCE
EDGE
G56K
CMS
GAP
DE
Bit
FE
ID * - Channel Control (for T1/J1) /
Backplane Global Configuration
RTSFS Change Indication
Timeslot Control (for E1)
RTSFS Interrupt Control
pin.
TBIF Operating Mode
TPLC Control Enable
TBIF Option Register
TBIF TS Offset
TBIF Bit Offset
Register
The
signaling
bits
T1/J1) / 00~1F (for E1)
TPLC ID * - 01~18 (for
0CC, 1CC, 2CC, 3CC,
4CC, 5CC, 6CC, 7CC
04C, 14C, 24C, 34C,
04B, 14B, 24B, 34B,
44C, 54C, 64C, 74C
44B, 54B, 64B, 74B
043, 143, 243, 343,
042, 142, 242, 342,
045, 145, 245, 345,
044, 144, 244, 344,
443, 543, 643, 743
442, 542, 642, 742
445, 545, 645, 745
444, 544, 644, 744
on
Address (Hex)
010
the
TSIGn/
88
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.19 TRANSMIT PAYLOAD CONTROL
mitted or the data stream to be transmitted can be extracted to the
PRBS Generator/Detector for test in this block.
PCCE bit must be set to ‘1’.
TSDn/MTSDA (MTSDB) pins on a per-channel/per-TS basis or on a
global basis of the corresponding link (the methods are arranged from
the highest to the lowest in priority):
Different test patterns can be inserted in the data stream to be trans-
To enable all the functions in the Transmit Payload Control, the
The following methods can be executed on the data input from the
• When the TESTEN bit is enabled and the PRBSDIR bit is ‘1’, the
• Configured by the ZCS[2:0] bits, four types of Zero Code Suppres-
• Selected by the GSUBST[2:0] bits, the data of all channels/
• Controlled by the SIGINS bit, the signaling bits input from the
• Invert the most significant bit, the even bits and/or the odd bits by
• When the TESTEN bit is enabled and the PRBSDIR bit is ‘0’, the
data to be transmitted will be extracted to the PRBS Generator/
Detector. The data to be transmitted can be extracted in unframed
mode, in 8-bit-based mode or in 7-bit-based mode. This selection
is made by the PRBSMODE[1:0] bits. In unframed mode, all the
data stream to be transmitted is extracted and the per-channel/per-
TS configuration in the TEST bit is ignored. In 8-bit-based mode or
in 7-bit-based mode, the data will only be extracted on the channel/
timeslot configured by the TEST bit. Refer to Chapter 3.27.1 PRBS
Generator / Detector for details.
sion can be selected to implement to the data of all the channels of
the corresponding link. This function is only supported in T1/J1
mode.
timeslots of the corresponding link will be replaced by the trunk
code set in the DTRK[7:0] bits, the milliwatt pattern defined in
Table 36 and Table 37, or the payload loopback data from the
Elastic Store Buffer (refer to Chapter 3.27.2.2 Payload Loopback).
When the GSUBST[2:0] bits are set to ‘000’, these replacements
will be performed on a per-channel/per-TS basis by setting the
SUBST[2:0] bits in the corresponding channel/timeslot.
TSIGn/MTSIGA (MTSIGB) pins (after processed by the signaling
trunk conditioning replacement and/or valid signaling bits selec-
tion) can be inserted into its signaling bit position of the data
stream to be transmitted.
setting the SINV, OINV, EINV bits.
data to be transmitted will be replaced by the test pattern gener-
ated from the PRBS Generator/Detector. The data to be transmit-
ted can be replaced in unframed mode, in 8-bit-based mode or in
7-bit-based mode. This selection is made by the PRBSMODE[1:0]
bits. In unframed mode, all the data stream to be transmitted is
replaced and the per-channel/per-TS configuration in the TEST bit
is ignored. In 8-bit-based mode or in 7-bit-based mode, the data
will only be replaced on the channel/timeslot configured by the
TEST bit. Refer to Chapter 3.27.1 PRBS Generator / Detector for
details.
March 04, 2009