82P2288BB8 IDT, Integrated Device Technology Inc, 82P2288BB8 Datasheet - Page 185
82P2288BB8
Manufacturer Part Number
82P2288BB8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82P2288BB8.pdf
(362 pages)
Specifications of 82P2288BB8
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
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T1/J1 Error Insertion (06FH, 16FH, 26FH, 36FH, 46FH, 56FH, 66FH, 76FH)
DDSINV:
CRCINV:
FsINV:
FtINV:
Programming Information
IDT82P2288
Bit Name
This bit is valid in T1 DM format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit wil invert one 6-bit DDS pattern.
This bit is cleared when the inversion is completed.
This bit is valid in ESF format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one 6-bit CRC pattern.
This bit is cleared when the invertion is completed.
In SF, T1 DM formats, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Fs bit (the F-bit in even frame).
In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Frame Alignment bit.
In SLC-96 format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Synchronization Fs bit.
This bit is cleared when the inversion is completed.
In SF, T1 DM, SLC-96 formats, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Ft bit (the F-bit in odd frame).
This bit is cleared when the inversion is completed.
Default
Bit No.
Type
7
6
Reserved
5
4
185
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
DDSINV
R/W
3
0
CRCINV
R/W
2
0
FsINV
R/W
1
0
March 04, 2009
FtINV
R/W
0
0
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