82P2288BB8 IDT, Integrated Device Technology Inc, 82P2288BB8 Datasheet - Page 48

• Manufacturer Part Number: 82P2288BB8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB8

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

synchronization again only if the Basic frame is in synchronization.
During out of CAS Signaling Multi-Frame synchronization state, the CAS
Signaling Multi-Frame Alignment Pattern Error detection is suspended.
3.8.2.3 Overhead Extraction
International Bit Extraction
Si[0:1] bits in the TS0 International / National register. The Si[0:1] bits in
the TS0 International / National register are updated on the boundary of
the associated FAS/NFAS frame and are held during out of Basic frame
state.
Remote Alarm Indication Bit Extraction
to the A bit in the TS0 International / National register. The A bit in the
TS0 International / National register is updated on the boundary of the
associated NFAS frame and is held during out of Basic frame state.
National Bit Extraction
Sa[4:8] bits in the TS0 International / National register. The Sa[4:8] bits
in the TS0 International / National register are updated on the boundary
of the associated NFAS frame and are held during out of Basic frame.
National Bit Codeword Extraction
the CRC Sub Multi-Frame, refer to Table 18) are extracted to the corre-
sponding SaX Codeword register. Here the ‘X’ is from 4 through 8. The
National Bit codeword extraction will be set to de-bounce if the SaDEB
bit is set to ‘1’. Thus, the SaX Codeword registers are updated if the
received National Bit codeword is the same for 2 consecutive CRC Sub
Multi-Frames. Whether de-bounced or not, a change indication will be
set in the SaXI bit (‘X’ is from 4 through 8) if the corresponding codeword
in the SaX Codeword register differs from the previous one.
Multi-Frame synchronization state.
Functional Description
IDT82P2288
The International bits (Si bits, refer to Table 18) are extracted to the
The Remote Alarm Indication bit (A bit, refer to Table 18) is extracted
The National bits (Sa bits, refer to Table 18) are extracted to the
The five sets of the National Bit codewords (Sa4[1:4] to Sa8[1:4] in
The value in the SaX Codeword registers is held during out of CRC
48
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Extra Bit Extraction
bits in the TS16 Spare register. The X[0:2] bits in the TS16 Spare
register are updated at the first bit of the next CAS Signaling Multi-
Frame and are held during out of CAS Signaling Multi-Frame state.
Remote Signaling Multi-Frame Alarm Indication Bit Extraction
Figure 13) are extracted to the Y bit in the TS16 Spare register. The Y bit
in the TS16 Spare register is updated at the first bit of the next CAS
Signaling Multi-Frame and is held during out of CAS Signaling Multi-
Frame state.
Sa6 Code Detection Per ETS 300 233
(MSB is the first received bit) are compared with 0x888, 0xAAA, 0xCCC,
0xEEE and 0xFFF. When CRC Multi-Frame is synchronized, any 3
consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are
compared if the Sa6SYN bit is ‘1’. If a matched code is detected, the
corresponding indication bit in the Sa6 Code Indication register will be
set.
3.8.2.4 V5.2 Link
detected with the indication in the V52LINKV bit. This detection is
disabled when the Basic Frame is out of synchronization.
3.8.2.5 Interrupt Summary
When there are conditions meeting the interrupt sources, the corre-
sponding Status bit will be asserted high. When there is a transition
(from ‘1’ to ‘0’ or from ‘0’ to ‘1’) on the Status bit, the corresponding
Status Interrupt Indication bit will be set to ‘1’ (If the Status bit does not
exist, the source will cause its Status Interrupt Indication bit to ‘1’
directly) and the Status Interrupt Indication bit will be cleared by a write
signal. A ‘1’ in the Status Interrupt Indication bit means an interrupt
occurred. The interrupt will be reported by the INT pin if its Status Inter-
rupt Enable bit is ‘1’.
The Extra bits (X bits, refer to Figure 13) are extracted to the X[0:2]
The Remote Signaling Multi-Frame Alarm Indication bit (Y bit, refer to
When Basic frame is synchronized, any 12 consecutive Sa6 bits
The V5.2 link ID signal, i.e., 2 out of 3 sliding Sa7 bits being logic 0, is
The interrupt sources in this block are summarized in Table 20.
March 04, 2009